8.2.1 Signal Output (VOUTP, VOUTN)

As shown in Figure 34, the DAC provides a differential voltage (V_DIFF = VOUTP – VOUTN) on pins VOUTP and VOUTN. The output common-mode voltage (V_COM) is regulated to 100 mV below the midpoint of the analog supply (AVDD – AVSS).

Each signal output swings above and below the common-mode voltage. Best performance is realized when the DAC output is used differentially. In power-down mode, the outputs enter a high-impedance, 3-state mode.

NOINDENT:

NOTE: V_DIFF = VOUTP – VOUTN = ±2.5 V × Gain (V_REF = 5 V).
V_COM = –0.1 V (±2.5-V supplies) or 2.4 V (5-V supply).

Figure 34. DAC Output Signal

The DAC output buffer is rated to drive up to a 2-nF capacitive load (maximum) and a 100-Ω resistive load (minimum). However, degradation of THD performance results in resistive loads less than 1 kΩ, as shown in Figure 26

The internal digital modulator generates the signal to drive the DAC. The modulator shapes the in-band noise to high frequency and the frequency-shaped noise is present on the DAC output. However, the high frequency DAC output noise is rejected by the digital filter of the ADC and does not affect system performance.

The DAC sampling update noise is also present on the signal output. The sampling noise does not affect the ADC performance, but when testing the ADC near full-scale input, the noise can cause false indication of the ADC modulator overrange detection. The ADS1282 overrange output signal indication should be ignored when testing at or below the ADC full-scale input.

8.2.2 DAC Modes

The DAC1282 has four operational modes of: sine, dc, pulse, and external digital data input. These modes are programmed by the MODE[1:0] bits in the GANMOD register, as shown in Table 1.

8.2.2.1 Sine Mode

In sine mode, the DAC1282 provides a sine-wave output. An internal signal generator develops the sine-wave signal. The M[3:0], N[7:0], and FREQ register bits program the output frequency. The frequency range is programmable from 0.4883 Hz to 250 Hz, as shown in Equation 1.

Equation 1.

where

1. f_CLK = 4.096 MHz. The signal frequency scales with f_CLK.

Table 2 lists values of registers M and N for selected output frequencies.

Table 2. Register Output Frequencies

SIGNAL FREQUENCY (Hz)(1)	M[3:0] REGISTER BITS	N[7:0] REGISTER BITS	FREQ BIT
0.48828125	0000	1111 1111	1
0.9765625	0000	1111 1111	0
1.953125	0000	0111 1111	0
3.90625	0000	0011 1111	0
7.8125	0000	0001 1111	0
15.625	0000	0000 1111	0
31.25	0000	0000 0111	0
50	0000	0000 0100	0
55	1010	0011 0001	0
60	0101	0001 1000	0
62.5	0000	0000 0011	0
100	1001	0001 1000	0
125	0000	0000 0001	0
250	0000	0000 0000	0

(1) f_CLK = 4.096MHz. The signal frequency scales with f_CLK.

When the M or N registers are updated, the sine wave resets to the zero-crossing point. The sine wave can also be reset to the zero-crossing point by taking the SYNC pin high; see the SYNC section.

The amplitude of the sine-wave output is determined by analog and digital gains. The analog gain increments are 6 dB, from 0 dB to –36 dB, and are programmed by the GAIN[2:0] register bits. Table 3 lists the analog gains.

Table 3. Analog Gain

ANALOG GAIN (V/V)(1)	ANALOG GAIN (dB)(3)	DIFFERENTIAL RANGE (V)(2)	GAIN[2:0] REGISTER BITS
1/1	0	±2.5	000
1/2	–6	±1.25	001
1/4	–12	±0.625	010
1/8	–18	±0.312	011
1/16	–24	±0.156	100
1/32	–30	±0.078	101
1/64	–36	±0.039	110

(1) The DAC1282A supports analog gains of 1/1, 1/4, and 1/16 only.

(2) V_REF = 5 V, digital gain = 0 dB.

(3) Relative to 1.77 V_RMS full-scale.

The digital gain resolution is in 0.5-dB increments, from 0 dB to full mute and is programmed by the SINEG[7:0] register bits. Table 4 lists the digital gain setting. Equation 2 is the amplitude setting in sine mode.

Equation 2. Sine Amplitude (dB) = Analog Gain (dB) + Digital Gain (dB)

Best SNR, for a given signal level, is achieved by reducing the analog gain while maximizing the digital gain.

Table 4. Sine Mode Digital Gain

SINE MODE DIGITAL GAIN (dB)	SINEG[7:0] REGISTER BITS
0	0000 0000
–0.5	0000 0001
–1.0	0000 0010
—	—
–119.5	1110 1111
Full mute	1111 0000
Full mute	1111 xxxx
Full mute	1111 1111

8.2.3 Reference Voltage (V_REF)

The DAC1282 requires an external reference for operation. Although reference voltage as low as 2.5 V can be used, best SNR is achieved with a 5-V reference. The reference input is defined as the voltage difference between VREF and AVSS (that is, V_REF = VREF – AVSS). The DAC1282 output scales with V_REF; consequently, reference noise or drift appears on the DAC output. Excessive reference noise may lead to degraded SNR. A low-drift and low-noise reference is recommended.

Connect the external reference ground pin directly to the AVSS pins using a star connector to AVSS pin 14. Star connection minimizes the possibility of power-supply crosstalk. Also, connect a 0.1-µF capacitor close to the VREF and AVSS terminals to reduce noise susceptibility. Figure 35 shows the reference connection. The reference input impedance is 220 kΩ. In power-down the switch is off, resulting in very high input impedance. For single-supply applications, connect AVSS to a clean analog ground point.

1.

NOINDENT:

Recommended bypass capacitor.

Figure 35. Reference Input Connection

8.2.4 Output Filter (CAPP, CAPN)

The CAPP and CAPN pins are the connections for two external capacitors, one capacitor connects to CAPP and VOUTP and the other capacitor connects to CAPN and VOUTN. The capacitors are required to filter the DAC sampling noise. The capacitor values are 1 nF; capacitors with low voltage coefficients should be used (C0G ceramic or film).

As seen in Figure 36, the external capacitors form an analog low-pass filter with the internal feedback resistors. After step changes to the data in the sine, dc, and digital data modes, the settling of the DAC and the analog filter is 100-µs typical, as shown in Figure 46. In pulse mode, the filter is internally disabled, yielding shorter settling time.

Figure 36. Output Filter

8.2.5 Output Switch (SWINP, SWINN, SWOUTP, SWOUTN)

The DAC1282 has an integrated output switch. The switch can be used to route the DAC output signal to a sensor for pulse, THD, and common-mode testing. The switch has low on-resistance and matched elements to minimize signal distortion. The switch input voltage range extends to the analog power supply.

The switch is controlled by three register bits, SW[2:0], and is also controlled by the SW/TD input pin. The switch integrates break-before-make operation when the register or the SW/TD input control is changed. The SW/TD input can be used to force the switch open for precise timing control of sensor impulse testing; see the Switch Control/DAC Data Input (SW/TD) section. Figure 37 and Table 8 describe the switch operation.

Figure 37. DAC1282 Signal Switch

Note that when the DAC is in power-down mode, the switch is forced open.

As shown in Figure 29, the switch on-resistance varies with the switch signal level. When the switch is used to route the signal and a resistive load is connected to the switch output, the switch on-resistance variations interact with the load resistance and cause the THD to degrade. Figure 27 illustrates the dependence of THD versus switch load resistance. The dependence of THD data was taken with a full-scale signal.

8.2.6 Clock Input (CLK)

The CLK pin is the master clock input to the DAC1282, nominally 4.096 MHz. As with any high-performance data converter, a high-quality clock source is essential. A crystal oscillator or low-jitter PLL clock source is recommended. Make sure to avoid ringing on the input by keeping the trace short and source-terminating (typically 50 Ω). See the CLK specifications shown in Figure 38 and Table 9.

Figure 38. CLK Timing Requirements

8.2.7 Switch Control/External Digital Input (SW/TD)

SW/TD is a multi-function digital input pin. The SW/TD function depends on the mode of operation.

8.2.8 SYNC

SYNC is a digital input used to synchronize the DAC1282 output.

In the digital data mode, the DAC input is a ones-density bitstream. In this mode, the SYNC pin synchronizes the sampling of SW/TD digital data to the desired master clock cycle (CLK). When SYNC is low or high, the DAC operates normally. When SYNC is taken from low to high, the DAC output is reset to zero and the sample instant of SW/TD is reset to the eighth rising CLK edge that follows. The SW/TD is then regularly sampled on subsequent 16 CLK intervals. After synchronization, the DAC output is not settled and achieves full settling 400 CLK periods later, as shown in Figure 39.

Figure 39. Digital Data Mode Synchronization

In sine mode, the SYNC rising edge resets the DAC output to differential 0 V (sine-wave zero-crossing point). When SYNC is high or low, the output is unaffected. When SYNC is taken from low to high, the output resets on the following CLK rising edge. SYNC must be pulsed low for a minimum of 2 CLK cycles. The SYNC input can be applied simultaneous to the DAC and the ADS1282 (ADC in pulse-sync mode).

To synchronize the DAC, observe SYNC to the CLK timing requirements shown in Figure 40. That is, the SYNC rising edge should be applied before the set-up time or after the hold time specifications. If the SYNC timing requirement is not met, the DAC may synchronize with one clock cycle timing error.

Figure 40. Sine Mode Synchronization

In pulse mode, the SYNC pin selects one of two pre-programmed pulse levels. The pulse levels are programmable from +2.5 V to –2.5 V in approximately 3-dB steps by pulse level registers PULSA and PULSB. When SYNC is low, the value of the PULSA register drives the DAC; when SYNC is high, the value of the PULSB register is the code of the DAC, as shown in Figure 41. When the SYNC pin is changed, the DAC output updates immediately to the new code.

Figure 41. Sync Operation in Pulse Mode

8.2.9 RESET/PWDN

The RESET/PWDN is a digital input used to power-down and reset the DAC1282. To power-down the DAC, take the pin low. In power-down mode, the power consumption is reduced to a device leakage level (see the Electrical Characteristics table). The signal output and digital pin DOUT enters 3-state and the output switch is driven off. Note that the digital inputs must remain defined as either logic low or logic high; do not float the inputs. Disable the CLK input to minimize leakage. To exit the power-down state, take the pin high. The DAC1282 is reset after power-down mode is exited.

The DAC1282 is reset by taking the RESET/PWDN pin low for a minimum of two f_CLK cycles and is then taken back high. The DAC1282 is held in reset for 2 f_CLK cycles; after this time, DAC communications may begin, as shown in Figure 42 and Table 12.

Figure 42. DAC RESET/PWDN

8.2.10 AVDD, AVSS, and DVDD Power Supplies

The DAC1282 has two power supplies: analog and digital. The analog supply (AVDD, AVSS) is 5 V and can either be single 5 V or dual (±2.5 V). The analog supply should be clean and free from noise and ripple. The DAC1282 regulates the output common-mode voltage to 0.1 V below the mid-point of the analog supply. Because the analog supply pins draw signal-dependent current and AVSS (pin 14) is internally shared with the reference input low, trace resistance between AVSS (pin 14) and the AVSS power supply should be minimized or degraded performance may result. Therefore, connect the external reference ground terminal close to the device AVSS terminal using a star connection. This configuration helps to minimize power-supply coupling to the reference input.

DVDD is the digital supply used to power both the internal digital and the device I/O pins. The allowable range of DVDD is 1.65 V to 3.6 V.

The power supplies can be sequenced on or off in any order, but the analog or digital inputs should never exceed AVDD or AVSS, or DVDD, respectively. In such an event, the internal ESD protection diodes may begin to conduct. The input current must always be limited as specified in the Absolute Maximum Ratings table.

At power-on, when the latter of DVDD exceeds approximately 1.3 V, or the difference of AVDD – AVSS exceeds approximately 1.4 V, an internal power-on reset (POR) occurs. During POR, the device is held in a reset condition for a period of 2¹⁶ f_CLK periods as shown in Figure 43. During this time, the DAC1282 output is held at 0 V, differential. SPI communications are not possible during this time. After the reset time elapses, the default settings are loaded: 31.25 Hz, 28 mV_RMS amplitude, and output switch off. SPI communications can then be started.

Figure 43. Power-On Sequence

8.2.11 Step Response

The step response of the DAC depends on the mode. In pulse mode, the DAC disables the external analog filter formed by capacitors CAPP, CAPN. Disabling the analog filter in conjunction with the fast response pulse DAC results in noticeably faster rise time and shorter settling time. Note that additional filter components in the signal path may also affect the response time.

Figure 44 shows the pulse mode step response after the SYNC pin transition. Figure 45 shows the pulse mode detail settling to 0.1% of final value after the SYNC pin transition.

Figure 44. Pulse Mode Step Response

Figure 45. Pulse-Mode, Step-Response Detail

Figure 46 shows the step response time of the dc mode. The step response of sine and digital data mode have similar settling times. Note that additional filter components in the signal path may also affect the response time.

Figure 46. DC-Mode Step Response

8.2.12 Frequency Response

The DAC internal signal generator is capable of output signal frequencies from 0.489 Hz to 250 Hz. Frequencies outside of this range are also possible by driving the DAC directly with an external digital input (bitstream). However, the DAC low-pass filters the digital input and results in a sinx/x frequency response. The –3 dB signal bandwidth of the DAC filter is 8.2 kHz. Figure 47 illustrates the DAC1282 frequency response. Note that high-order noise-shaped digital inputs may limit the useable frequency range as a result of rising noise.

Figure 47. DAC Frequency Response

8.3.1 Serial Interface

Configuration of the DAC is by an SPI-compatible serial interface consisting of four signals: CS, SCLK, DIN, and DOUT; or the interface can consist of three signals in which case CS may be tied low. Tying CS low permanently selects the device and DOUT remains a driven output. The interface is used to read and write registers and also is used to send a DAC reset command.

8.3.2 SPI Timeout

The DAC has an SPI timeout feature that can be used to recover the SPI port if a possible noise pulse should occur. The noise pulse may lead to a false SCLK detection that can render the DAC serial port unresponsive. The port is recovered by taking CS high but, in applications where CS is tied low, holding SCLK low for 2¹⁸ CLK cycles resets the SPI port automatically. When SCLK is low, the SPI port resets on every 2¹⁸ CLK cycle interval. Holding SCLK high disables the automatic SPI reset.

8.4.1 Commands

The commands summarized in Table 14 control and configure the DAC1282. The register read and register write commands are two-byte command arguments plus additional data bytes while the reset command is a one-byte command. The DAC1282 serial port chip select (CS) can be taken high or held low between commands but must remain low for the entire command operation.

8.4.1.1 RREG: Read From Registers

Description: These two opcode bytes read register data. The register read operation is a two-byte opcode input followed by one or more bytes of register data as the output. The first byte of the command is the opcode and the register address combined. The second byte of the command specifies the number of registers to read (minus 1) in a block. Register data are output following the command input. Note that for multiple register read operations, the register address pointer does not wrap when the last register is exceeded.

First opcode byte: 0010 rrrr, where rrrr is the starting address register address to be read.

Second opcode byte: 0000 nnnn, where nnnn is the number of registers to read – 1.

Following bytes: Register data output in MSB-first format. The 16th SCLK falling edge of the opcode clocks out the MSB of the register data.

1. CS may be tied low.

Figure 48. RREG Command Example: Read Two Registers Starting from Register 00h
(Opcode 1 = 0010 0000, Opcode 2 = 0000 0001)

8.4.1.2 WREG: Write To Registers

Description: These two opcode bytes write register data. The register write operation is a two-byte opcode followed by one or more bytes of register data. The first byte of the command is the write opcode and the register address combined. The second byte of the command specifies the number of registers to write (minus 1) in a single sequence. The following bytes are the register data bytes. Note that for multiple register write operations, the register address pointer does not wrap when the last register is exceeded.

First opcode byte: 0010 rrrr, where rrrr is the starting address register address to be written.

Second opcode byte: 0000 nnnn, where nnnn is the number of registers to write – 1.

Following bytes: Register data input in MSB-first format.

1. CS may be tied low.

Figure 49. WREG Command Example: Write Two Registers Starting from Register 00h
(Opcode 1 = 0100 0000, Opcode 2 = 0000 0001)

Table 15. Register Map

8.5.1 Register Descriptions