8.3.1.1 Loop Error

A loop error occurs when the device is unable to sustain the required output current at OUT pin, typically caused by a drop in loop supply, or an increase in load impedance.

When a loop error occurs, the DAC161S997 changes the OUT-pin current to the value in the ERROR_LOW register, unless the MASK_LOOP_ERR is set to 1. If the MASK_LOOP_ERR is not set, then the device also periodically attempts to reassert the OUT current set in DACCODE by default. If the DACCODE-current output is set, the DAC161S997 then stops reporting a loop error. The interval between reasserts is controlled by the L_RETRY_TIME field in the ERROR_CONFIG register. If the DIS_RETRY_LOOP field in the ERROR_CONFIG register is changed to 1, the device does not periodically check the loop and, instead, only checks the loop after a read of the ERR_STATUS (0x09) register. If the loop error is not resolved, then the loop-error current persists.

When a loop error occurs, the DAC161S997 sets the CURR_LOOP_STATUS and LOOP_STATUS fields in the STATUS register to 1. The LOOP_STATUS field remains set to 1 until the STATUS register is read or the device is reset. If the loop error is cleared, either by the device reasserting the loop current or by changing the OUT current , then the CURR_LOOP_STATUS field clears.

8.3.1.2 SPI Timeout Error (Channel Error)

The DAC161S997 expects to receive periodic SPI write commands to ensure that the SPI connection is functioning normally. If no SPI write command occurs within the time indicated by the SPI_TIMEOUT field in the ERROR_CONFIG register, the device reports a SPI timeout error. Note that the SPI write command must be properly formatted to avoid SPI Timeout errors (such as a write command that generates a frame error does not prevent an imminent SPI Timeout error).

SPI Timeout error reporting is inhibited by MASK_SPI_TOUT. SPI Timeout errors are not reported on the loop if MASK_SPI_ERR is set to 1.

Note that a write command to address 0 is not considered a valid write command and will not prevent a SPI Timeout error.

8.3.1.3 Frame Error

If a SPI write command has an incorrect number of SCLK pulses, the device reports a frame error. The number of SCLK pulses must be an integer and a multiple of 24. A frame error is always reported by ERRB being pulled low. A frame error does not affect the loop current.

8.3.1.4 Alarm Current

By default, the DAC161S997 reports faults to the plant controller by forcing the OUT current into one of two error bands. The error current bands are defined as either greater than 20 mA, or less than 4 mA. Loop errors are reported by setting current of ERR_LOW.

If SPI Timeout Errors are reported on the loop (this is the default; it can be changed by setting the register ERR_CONFIG:MASK_LOOP_ERR), the error band is controlled by the ERRLVL pin. When ERRLVL is tied to the COMD voltage, the ERR_LOW current is the reporting current. If ERRLVL is tied to VD then the ERR_HIGH current is the current-on pin, OUT, if a SPI timeout error occurs.

The exact value of the output current used to indicate fault is dictated by the contents of ERR_HIGH and ERR_LOW registers.

In the case of a conflicting alarm-current setting (such as a loop error and SPI timeout error occurring simultaneously and ERRLVL is tied high), the current-on pin, OUT, is determined by ERR_LOW current.

8.5.1.1 SPI Write

SPI write operation is used to change the state of the device. Handshaking does not occur between the master and the slave (DAC161S997), and the master must control the communication on the following inputs: SCLK, CSB, SDI. The format of the data transfer is described in the Serial Interface section.

A write is composed of two sections, 8-bits corresponding to a command and 16-bits of data. A command is simply the address of the desired register to update. Note that some registers are read-only; a write to these registers will have no effect on the device operation and the register contents will not change. The user instruction set is shown in the Detailed Description section.

During power up or device reset, the register contents of all writable registers are set to the listed values in the Detailed Description section.

If the DAC161S997 is used in a highly noisy environment in which SPI errors are potentially an issue, the DAC161S997 supports a more robust protocol (see Optional Protected SPI Writes).

8.5.1.2 SPI Read

The read operation requires all 4 wires of the SPI interface, which are SCLK, SCB, SDI, and SDO. The simplest READ operation occurs automatically during any valid transaction on the SPI bus because the SDO pin of DAC161S997 always shifts out the contents of the internal FIFO. Therefore the data being shifted in to the FIFO is verified by initiating another transaction and acquiring data at SDO, allowing only for the verification of FIFO contents.

The internal registers are accessed by the user through a register read command. A register read command is formed by setting bit 7 of the command to 1 (effectively ORing with 0x80) with the address of the desired register to be read and sending the resulting 8 bits as the command (see Detailed Description). For example, the register read command of the STATUS register (address 0x05) would be 0x85.

A register read requires two SPI transactions to recover the register data. The first transaction shifts in the register read command; an 8-bits of command byte followed by 16-bits of dummy data. The register read command transfers the contents of the internal register into the FIFO. The second transaction shifts out the FIFO contents; an 8-bit command byte (which is a copy of previous transaction) followed by the register data. The Register Read operation is shown in Figure 10.

Figure 10. SPI Register Read Operation

8.5.1.3 Optional Protected SPI Writes

The DAC161S997 supports an optional SPI protocol intended to provide robust support against SPI write errors.

When PROTECT_REG_WR is set to 1, all register writes require a subsequent XFER_REG command (a write of 0x00FF to XFER_REG[0x01]) to load the transferred data into the register address (see Figure 11). This requirement provides protection against write errors in an electrically noisy environment.

Figure 11. Protected SPI writes

8.5.1.3.1 SPI Write Error Correction

To minimize the chance of a SPI write error, TI recommends to append a NOP command onto the end of every register write sequence to verify that the XFER_REG is properly executed, as shown in Figure 12.

Figure 12. Protected SPI writes with NOP command

The XFER_REG command combined with the automatic SDO loopback of the previous SPI write data prevents loading of incorrect data into a register. If the loopback indicates a communication error has occurred (see Figure 13), the CSB pin is held low and the previous write command is repeated. Although the second SPI transaction had 48 SCLK pulses instead of 24 pulses, this is not considered a frame error. A frame error is indicated when the number of SCLK pulses is not an integer multiple of 24.

Figure 13. Detection of Error in Register Load

If a communication error occurs in the XFER_REG command, it is detected during the trailing NOP command (see Figure 14). Although the register load is incomplete, the device has not changed operations. Repeat the original data and XFER_REG command.

Figure 14. Detection of Error in Register Readback