7.3.1 Serdes Input

The RX[7:0]P/N differential inputs are each internally terminated to a common point via 50Ω, as shown in
Figure 55.

Common mode termination is via a 50pF capacitor to GND. The common mode voltage and termination of the differential signal can be controlled in a number of ways to suit a variety of applications via rw_cfgrx0 [10:8] (TERM), as described in Table 1.
(Note: AC coupling is recommended for JESD204B compliance.)

Data input is sampled by the differential sensing amplifier using clocks derived from the clock recovery algorithm. The polarity of RXP and RXN can be inverted by setting the INVPAIR [7:0] bit of the corresponding lane to “1”. This can potentially simplify PCB layout and improve signal integrity by avoiding the need to swap over the differential signal traces.

Due to processing effects, the devices in the RXP and RXN differential sense amplifiers will not be perfectly matched and there will be some offset in switching threshold. DAC38J82/DAC37J82 family contains circuitry to detect and correct for this offset. This feature can be enabled by setting the rw_cfgrx0 [23] (ENOC) bit to “1”. It is anticipated the most users will enable this feature. During the compensation process, rw_cfgrx0 [25:24] (LOOPBACK) bit must be set to “00”.

7.3.2 Serdes Rate

The DAC37J82/DAC38J82 has 8 configurable JESD204B serial lanes. The highest speed of each SerDes lane is 12.5Gbps. Because the primary operating frequency of the SerDes is determined by its reference clock and PLL multiplication factor, there is a limit on the lowest SerDes rate supported, refer to Table 2 for details. To support lower speed application, each receiver should be configured to operate at half, quarter or eighth of the full rate via rw_cfgrx0 [6:5] (RATE).

7.3.3 Serdes PLL

The DAC37J82/DAC38J82 has two integrated PLLs, one PLL is to provide the clocking of DAC, which will be discussed in a DAC PLL section; the other PLL is to provide the clocking for the high speed SerDes. The reference frequency of the SerDes PLL can be in the range of 100-800MHz nominal, and 300-800MHz optimal.

The reference frequency is derived from DACCLK divided down based on the serdes_refclk_div programming, as shown in Figure 56.

During normal operation, the clock generated by PLL will be 4-25 times the reference frequency, according to the multiply factor selected via rw_cfgpll [8:1] (MPY). In order to select the appropriate multiply factor and refclkp/n frequency, it is first necessary to determine the required PLL output clock frequency. The relationship between the PLL output clock frequency and the lane rate is shown in Table 3. Having computed the PLL output frequency, the reference frequency can be obtained by dividing this by the multiply factor specified via MPY.

NOTE

High multiplication factor settings will be especially sensitive to reference clock jitter and should not be employed without prior consultation with TI.

The wide range of multiply factors combined with the different rate modes means it will often be possible to achieve a given line rate from multiple different reference frequencies. The configuration which utilizes the highest reference frequency achievable is always preferable.

The SerDes PLL VCO must be in the nominal range of 1.5625 - 3.125 GHz. It is necessary to adjust the loop filter depending on the operating frequency of the VCO. To indicate the selection the user must set the rw_cfgpll [9] (VRANGE) bit. If the PLL output frequency is below 2.17GHz, VRANGE should be set high.

Performance of the integrated PLL can be optimized according to the jitter characteristics of the reference clock by setting the appropriate loop bandwidth via rw_cfgpll [12:11] (LB) bits. The loop bandwidth is obtained by dividing the reference frequency by BWSCALE, where the BWSCALE is a function of both LB and PLL output frequency as shown in Table 5.

An approximate loop bandwidth of 8–30MHz is suitable and recommended for most systems where the reference clock is via low jitter clock input buffer. For systems where the reference clock is via a low jitter input cell, but of low quality, an approximate loop bandwidth of less than 8MHz may offer better performance. For systems where the reference clock is cleaned via an ultra low jitter LC-based cleaner PLL, a high loop bandwidth up to 60MHz is more appropriate. Note that the use of ultra high loop bandwidth setting is not recommended for PLL multiply factor of less than 8.

A free running clock output is available when rw_cfgpll [15:14] (ENDIVCLK) is set high. It runs at a fixed divided-by-5 of the PLL output frequency and has a duty cycle of 50%. A divided-by-16 of this free running clock can be configured to come out the alarm pin during digital test, see dtest [11:8] for the specific configuration needed.

7.3.4 Serdes Equalizer

All channels of the DAC37J82/DAC38J82 incorporate an adaptive equalizer, which can compensate for channel insertion loss by attenuating the low frequency components with respect to the high frequency components of the signal, thereby reducing inter-symbol interference. Figure 57 shows the response of the equalizer, which can be expressed in terms of the amount of low frequency gain and the frequency up to which this gain is applied (i.e., the frequency of the ’zero’). Above the zero frequency, the gain increases at 6dB/octave until it reaches the high frequency gain.

The equalizer can be configured via rw_cfgrx0[21:19] (EQ) and rx_cfgrx0[22] (EQHLD). Table 6 and Table 7 summarize the options. When enabled, the receiver equalization logic analyzes data patterns and transition times to determine whether the low frequency gain should be increased or decreased. The decision logic is implemented as a voting algorithm with a relatively long analysis interval. The slow time constant that results reduces the probability of incorrect decisions but allows the equalizer to compensate for the relatively stable response of the channel. The lock time for the adaptive equalizer is data dependent, and so it is not possible to specify a generally applicable absolute limit. However, assuming random data, the maximum lock time will be 6x10⁶ divided by the CDR activity level. For CDR (rw_cfgrx0[18:16]) = 110, this is 1.5x10⁶UI.

When EQ[2] = 0, finer control of gain boost is available using the EQBOOSTi IEEE1500 tuning chain field, as shown in Table 8.

When EQ is set to 010 or 011, the equalizer is reconfigured to provide analytical data about the amount of pre and post cursor equalization respectively present in the received signal. This can in turn be used to adjust the equalization settings of the transmitting link partner, where a suitable mechanism for communicating this data back to the transmitter exists. Status information is provided viadtest[11:8] (EQOVER, EQUNDER), by using the following method:

1. Enable the equalizer by setting EQHLD low and EQ to 001. Allow sufficient time for the equalizer to adapt;
2. Set EQHLD to 1 to lock the equalizer and reset the adaption algorithm. This also causes both EQOVER and EQUNDER to become low;
3. Wait at least 48UI, and proportionately longer if the CDR activity is less than 100%, to ensure the 1 on EQHLD is sampled and acted upon;
4. Set EQ to 010 or 011, and EQHLD to 0. The equalization characteristics of the received signal are analysed (the equalizer response will continue to be locked);
5. Wait at least 150×10³UI to allow time for the analysis to occur, proportionately longer if the CDR activity is less than 100%;
6. Examine EQOVER and EQUNDER for results of analysis.
   • If EQOVER is high, it indicates the signal is over equalized;
   • If EQUNDER is high, it indicates the signal is under equalized;
7. Set EQHLD to 1;
8. Repeat items 3–7 if required;
9. Set EQ to 001, and EQHLD to 0 to exit analysis mode and return to normal adaptive equalization.

Note that when changing EQ from one non-zero value to another, EQHLD must already be 1. If this is not the case, there is a chance the equalizer could be reset by a transitory input state (i.e., if EQ is momentarily 000). EQHLD can be set to 0 at the same time as EQ is changed.

As the equalizer adaption algorithm is designed to equalize the post cursor, EQOVER or EQUNDER will only be set during post cursor analysis if the amount of post cursor equalization required is more or less than the adaptive equalizer can provide.

7.3.5 JESD204B Descrambler

The descrambler is a 16-bit parallel self-synchronous descrambler based on the polynomial 1 + x¹⁴ + x¹⁵. From the JESD204B specification, the scrambling/descrambling process only occurs on the user data, not on the code group synchronization or the ILA sequence. The descrambler output can be selected to sent out during JESD test, see jesd_testbus_sel for the specific configuration needed.

7.3.6 JESD204B Frame Assembly

The JESD204B defines the following parameters:

• L is the number of lanes per link
• M is the number of converters per device
• F is the number of octets per frame clock period
• S is the number of samples per frame
• HD is the High-Density bit which controls whether a sample may be divided over more lanes.

Table 9 list the available JESD204B formats for the DAC37J82/DAC38J82. Table 10 and Table 11 list the speed limits of DAC38J82/DAC37J82. The ranges are limited by the Serdes PLL VCO frequency range, the Serdes PLL reference clock range, the maximum Serdes line rate, and the maximum DAC sample frequency.

7.3.7 Serial Peripheral Interface (SPI)

The serial port of the DAC37J82/DAC38J82 is a flexible serial interface which communicates with industry standard microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the operating modes of the DAC37J82/DAC38J82. It is compatible with most synchronous transfer formats and can be configured as a 3 or 4 pin interface by sif4_ena in register config2. In both configurations, SCLK is the serial interface input clock and SDENB is serial interface enable. For 3 pin configuration, SDIO is a bidirectional pin for both data in and data out. For 4 pin configuration, SDIO is bidirectional and SDO is data out only. Data is input into the device with the rising edge of SCLK. Data is output from the device on the falling edge of SCLK.

Each read/write operation is framed by signal SDENB (Serial Data Enable Bar) asserted low. The first frame byte is the instruction cycle which identifies the following data transfer cycle as read or write as well as the 7-bit address to be accessed. Table 12 indicates the function of each bit in the instruction cycle and is followed by a detailed description of each bit. The data transfer cycle consists of two bytes.

Figure 58 shows the serial interface timing diagram for a DAC37J82/DAC38J82 write operation. SCLK is the serial interface clock input to the DAC37J82/DAC38J82. Serial data enable SDENB is an active low input to the DAC37J82/DAC38J82. SDIO is serial data in. Input data to the DAC37J82/DAC38J82 is clocked on the rising edges of SCLK.

Figure 59 shows the serial interface timing diagram for a DAC37J82/DAC38J82 read operation. SCLK is the serial interface clock input to the DAC37J82/DAC38J82. Serial data enable SDENB is an active low input to the DAC37J82/DAC38J82. SDIO is serial data in during the instruction cycle. In 3 pin configuration, SDIO is data out from the DAC37J82/DAC38J82 during the data transfer cycle, while SDO is in a high-impedance state. In 4 pin configuration, both SDIO and SDO are data out from the DAC37J82/DAC38J82 during the data transfer cycle. At the end of the data transfer, SDIO and SDO will output low on the final falling edge of SCLK until the rising edge of SDENB when they will 3-state.

In the SIF interface there are four types of registers:

• NORMAL: The NORMAL register type allows data to be written and read from. All 16-bits of the data are registered at the same time. There is no synchronizing with an internal clock thus all register writes are asynchronous with respect to internal clocks. There are three subtypes of NORMAL:
  • AUTOSYNC: A NORMAL register that causes a sync to be generated after the write is finished. These are used when it is desirable to synchronize the block after writing the register or in the case of a single field that spans across multiple registers. For instance, the NCO requires three 16-bit register writes to set the frequency. Upon writing the last of these registers an autosync is generated to deliver the entire field to the NCO block at once, rather than in pieces after each invidiual register write. For a field that spans multiple registers, all non-AUTOSYNC registers for the field must be written first before the actual AUTOSYNC register.
  • No RESET Value: These are NORMAL registers, but the reset value cannot be guaranteed. This could be because the register has some read_only bits or some internal logic partially controls the bit values.
• READ_ONLY: Registers that can be read from but not written to.
• WRITE_TO_CLEAR: These registers are just like NORMAL registers with one exception. They can be written and read, however, when the internal logic asynchronously sets a bit high in one of these registers, that bit stays high until it is written to ‘0’. This way interrupts will be captured and stay constant until cleared by the user. In the DAC37J82/DAC38J82, register config100-108 are WRTE_TO_CLEAR registers.

7.3.8 Multi-Device Synchronization

In many applications, such as multi antenna systems where the various transmit channels information is correlated, it is required that the latency across the link is deterministic and multiple DAC devices are completely synchronized such that their outputs are phase aligned. The DAC37J82/DAC38J82 achieves the deterministic latency using SYSREF (JESD204B Subclass 1).

SYSREF is generated from the same clock domain as DACCLK, and is sampled at the rising edges of the device clock. It can be periodic, single-shot or “gapped” periodic. After having resynchronized its local multiframe clock (LMFC) to SYSREF, the DAC will request a link re-initialization via SYNC interface. Processing of the signal on the SYSREF input can be enabled and disabled via the SPI interface.

7.3.9 Input Multiplexer

The DAC37J82/DAC38J82 includes a multiplexer after the JESD204B interface that allows any input stream A-B to be routed to any signal cannel A-B. See pathx_in_sel for details on how to configure the cross-bar switches.

7.3.10 FIR Filters

Figure 60 through Figure 63 show the magnitude spectrum response for the FIR0, FIR1, FIR2 and FIR3 interpolating filters where f_IN is the input data rate to the FIR filter. Figure 64 to Figure 67 show the composite filter response for 2x, 4x, 8x and 16x interpolation. The transition band for all interpolation settings is from 0.4 to 0.6 x f_DATA (the input data rate to the device) with < 0.001dB of pass-band ripple and > 90 dB stop-band attenuation.

The DAC37J82/DAC38J82 includes a no interpolation 1x mode. However, the input data rate in this mode is limited to 1230MSPS. See more details in Table 10 and .

The DAC37J82/DAC38J82 also has a 9-tap inverse sinc filter (FIR4) that runs at the DAC update rate (f_DAC) that can be used to flatten the frequency response of the sample-and-hold output. The DAC sample-and-hold output sets the output current and holds it constant for one DAC clock cycle until the next sample, resulting in the well-known sin(x)/x or sinc(x) frequency response (Figure 68, red line). The inverse sinc filter response (Figure 68, blue line) has the opposite frequency response from 0 to 0.4 x F_dac, resulting in the combined response (Figure 68, green line). Between 0 to 0.4 x f_DAC, the inverse sinc filter compensates the sample-and-hold roll-off with less than 0.03 dB error.

The inverse sinc filter has a gain > 1 at all frequencies. Therefore, the signal input to FIR4 must be reduced from full scale to prevent saturation in the filter. The amount of back-off required depends on the signal frequency, and is set such that at the signal frequencies the combination of the input signal and filter response is less than 1 (0 dB). For example, if the signal input to FIR4 is at 0.25 x f_DAC, the response of FIR4 is 0.9 dB, and the signal must be backed off from full scale by 0.9 dB to avoid saturation. The gain function in the QMC blocks can be used to reduce the amplitude of the input signal. The advantage of FIR4 having a positive gain at all frequencies is that the user is then able to optimize the back-off of the signal based on its frequency.

The filter taps for all digital filters are listed in Table 14. Note that the loss of signal amplitude may result in lower SNR due to decrease in signal amplitude.

7.3.11 Full Complex Mixer

The DAC37J82/DAC38J82 has two full complex mixer (FMIX) blocks with independent Numerically Controlled Oscillators (NCO) that enables flexible frequency placement without imposing additional limitations in the signal bandwidth. The NCOs have 48-bit frequency registers (phaseaddab(47:0) and phaseaddcd(47:0)) and 16-bit phase registers (phaseoffsetab(15:0) and phaseoffsetcd(15:0)) that generate the sine and cosine terms for the complex mixing. The NCO block diagram is shown in Figure 69.

Synchronization of the NCOs occurs by resetting the NCO accumulators to zero. The synchronization source is selected by syncsel_NCO(3:0) in config31. The frequency word in the phaseaddab(47:0) and phaseaddcd(47:0) registers is added to the accumulators every clock cycle, f_DAC. The output frequency of the NCO is

Treating the two complex channels in the DAC37J82/DAC38J82 as complex vectors of the form I + j Q, the output of FMIX I_OUT(t) and Q_OUT(t) is

I_OUT(t) = (I_IN(t)cos(2πf_NCOt + δ) – Q_IN(t)sin(2πf_NCOt + δ)) x 2^{(mixer_gain – 1)}

Q_OUT(t) = (I_IN(t)sin(2πf_NCOt + δ) + Q_IN(t)cos(2π f_NCOt + δ)) x 2^{(mixer_gain – 1)}

where t is the time since the last resetting of the NCO accumulator, δ is the phase offset value and mixer_gain is either 0 or 1. δ is given by:

δ = 2π × phase_offsetAB/CD(15:0)/2¹⁶

A block diagram of the mixer is shown in Figure 70. The complex mixer can be used as a digital quadrature modulator with a real output simply by only using the I_OUT branch and ignoring the Q_OUT branch.

The maximum output amplitude of FMIX occurs if I_IN(t) and Q_IN(t) are simultaneously full scale amplitude and the sine and cosine arguments are equal to 2π × f_NCOt + δ (2N-1) x π/4 (N = 1, 2, ...).

With mixer_gain = 0 in config2, the gain through FMIX is sqrt(2)/2 or –3 dB. This loss in signal power is in most cases undesirable, and it is recommended that the gain function of the QMC block be used to increase the signal by 3 dB to compensate. With mixer_gain = 1, the gain through FMIX is sqrt(2) or +3 dB, which can cause clipping of the signal if I_IN(t) and Q_IN(t) are simultaneously near full scale amplitude and should therefore be used with caution.

7.3.12 Coarse Mixer

In addition to the full complex mixers the DAC37J82/DAC38J82 also has a coarse mixer block capable of shifting the input signal spectrum by the fixed mixing frequencies ±n × f_S/8. Using the coarse mixer instead of the full mixers will result in lower power consumption.

Treating the two complex channels as complex vectors of the form I(t) + j Q(t), the outputs of the coarse mixer, I_OUT(t) and Q_OUT(t) are equivalent to:

I_OUT(t) = I(t)cos(2πf_CMIXt) – Q(t)sin(2πf_CMIXt)

Q_OUT(t) = I(t)sin(2πf_CMIXt) + Q(t)cos(2πf_CMIXt)

where f_CMIX is the fixed mixing frequency selected by cmix=(fs8, fs4, fs2, fsm4). The mixing combinations are described in Table 14.

7.3.13 Dithering

The DAC37J82/DAC38J82 supports the addition of a band limited dither to the DAC output after the complex mixer. This feature is enabled by set dither_ena to “1” and can be useful in reducing the high order harmonics. The generated dithering sequence can be optionally up-converted to an offset of Fs/2 by setting dither_mixer_ena to “1”. The added dithering sequence has variable amplitude in 6 dB steps via dither_sra_sel.

7.3.14 Complex Summation

The DAC37J82/DAC38J82 has a complex summation block which is to sum channel A with channel C, channel B with Channel D, and the resulted complex summation are divided by 2 and sent via channel A and channel B. This feature is enabled by set output_sum to “1” and can be useful for multi-band application.

7.3.15 Quadrature Modulation Correction (QMC)

7.3.16 Group Delay Correction Block

A complex transmitter system typically is consisted of a DAC, reconstruction filter network, and I/Q modulator. Besides the gain and phase mismatch contribution, there could also be timing mismatch contribution from each components. For instance, the timing mismatch could come from the PCB trace length variation between the I and Q channels and the group delay variation from the reconstruction filter. This timing mismatch in the complex transmitter system creates phase mismatch that varies linearly with respect to frequency. To compensate for the I/Q imbalances due to this mismatch, the DAC37J82/DAC38J82 has group delay correction block for each DAC channel.

The DAC38J82/DAC37J82 incorporates 2 FIR filters for small fractional group delay and 4 FIR filters for large fractional group delay. The input data to this block consists of 2, complex data (I/Q) channels i.e. 4 buses of 16-bit data. Control bits from configuration registers select the data path for all inputs through this block. Each input can either go through the small fractional delay filter (while its conjugate part goes through the matched delay line) or bypass the small fractional delay sub-block completely (matched delay line is bypassed for the conjugate part). The input to the large fractional delay F can either come from the output of small fractional delay sub-block or the original input to the block. The large fractional delay sub-block can also be completely bypassed if desired.

The DAC38J82/DAC37J82 also include an integer delay block following each large fractional group delay filter, which can further delay the DAC output by [0-3]×Tdac. Channel A&B share the same control signal output_delayab, and channel C&D share the same control signal output_delaycd, which means that channel A&B have the same integer delay, and channel C&D have the same integer delay.

7.3.17 Output Multiplexer

The DAC37J82/DAC38J82 family provides four analog outputs and includes an output multiplexer before the digital to analog converters that allows any signal channel to be routed to any analog outputs. See pathx_out_sel for details on how to configure the cross-bar switches.

7.3.18 Power Measurement And Power Amplifier Protection

The DAC37J82/DAC38J82 provides an optional mechanism to protect the Power Amplifier (PA) in cases when the signal power shows some abnormality. For example, if the data clock is lost, the FIFO would automatically generate a single tone signal, which causes abnormally high average power and could be dangerous to the PA. In the PA protection mechanism, the signal power is monitored by maintaining an sliding window accumulation of last N samples. N is selectable to be 64 or 128 based on the setting of pap_dlylen_sel. The average amplitude of input signal is computed by dividing accumulated value by the number of samples in the delay-line (N). The result is then compared against a threshold (pap_vth). If the threshold is violated, the delayed input signal is divided by a value chosen by pap_gain, to form a scaled down version of the input signal. Since PAP output derives from a delay-line, there is deterministic latency of at least N cycles from the block input to block output. The PA protection is enabled by setting the pap_ena bit to “1”.

7.3.19 Serdes Test Modes

The DAC37J82/DAC38J82 supports a number of basic pattern generation and verification of SerDes via SIF. Three pseudo random bit stream (PRBS) sequences are available, along with an alternating 0/1 pattern and a 20-bit user-defined sequence. The 2⁷-1,2³¹-1 or 2²³-1 sequences implemented can often be found programmed into standard test equipment, such as a Bit Error Rate Tester (BERT). Pattern generation and verification selection is via the TESTPATT fields of rw_cfgrx0[14:12], as shown in Table 18.

Pattern verification compares the output of the serial to parallel converter with an expected pattern. When there is a mismatch, the TESTFAIL bit is driven high, which can be programmed to come out the ALARM pin by setting dtest[3:0] to “0011”.

The DAC37J82/DAC38J82 also provide a number of advanced diagnostic capabilities controlled by the IEEE 1500 interface. These are:

• Accumulation of pattern verification errors;
• The ability to map out the width and height of the receive eye, known as Eye Scan;
• Real-time monitoring of internal voltages and currents;

The SerDes blocks support the following IEEE1500 instructions:

The data for each SerDes instruction is formed by chaining together sub-components called head, body (receiver or transmitter) and tail. The DAC37J82/DAC38J82 uses two SerDes receiver blocks R0 and R1, each of which contains 4 receive lanes (channels), the data for each IEEE1500 instruction is formed by chaining {head, receive lane 0, receive lane 1, receive lane 2, receive lane 3, tail}. A description of bits in head, body and tail for each instruction is given as follows:

NOTE

All multi-bit signals in each chain are packed with bits reversed e.g. mpy[7:0] in ws_core head subchain is packed as {retime, enpll, mpy[0:7], vrange,lb[0:1]}. All DATA REGISTER READS from SerDes Block R0 should read 1 bit more than the desired number of bits and discard the first bit received on TDO e.g., to read 40-bit data from R0 block, 41 bits should be read off from TDO and the first bit received should be discarded. Similarly, any data written to SerDes Block R0 Data Registers should be prefixed with an extra 0.

7.3.20 Error Counter

All receive channels include a 12-bit counter for accumulating pattern verification errors. This counter is accessible via the ECOUNT IEEE1500 Char field. It is an essential part of the eye scan capability (see next section), though can be used independently of this..

The counter increments once for every cycle that the TESTFAIL bit is detected. The counter will not increment when at its maximum value (i.e., all 1s). When an IEEE1500 capture is performed, the count value is loaded into the ECOUNT scan elements (so that it can be scanned out), and the counter is then reset, provided ENCOR is set high.

ECOUNT can be used to get a measure of the bit error rate. However, as the error rate increases, it will become less accurate due to limitations of the pattern verification capabilities. Specifically, the pattern verifier checks multiple bits in parallel (as determined by the Rx bus width), and it is not possible to distinguish between 1 or more errors in this.

7.3.21 Eye Scan

All receive channels provide features which facilitate mapping the received data eye or extracting a symbol response. A number of fields accessible via the IEEE1500 Char scan chain allow the required low level data to be gathered. The process of transforming this data into a map of the eye or a symbol response must then be performed externally, typically in software.

The basic principle used is as follows:

• Enable dedicated eye scan input samplers, and generate an error when the value sampled differs from the normal data sample;
• Apply a voltage offset to the dedicated eye scan input samplers, to effectively reduce their sensitivity;
• Apply a phase offset to adjust the point in the eye that the dedicated eye scan data samples are taken;
• Reset the error counter to remove any false errors accumulated as a result of the voltage or phase offset adjustments;
• Run in this state for a period of time, periodically checking to see if any errors have occurred;
• Change voltage and/or phase offset, and repeat.

Alternatively, the algorithm can be configured to optimize the voltage offset at a specified phase offset, over a specified time interval.

Eye scan can be used in both synchronous and asynchronous systems, while receiving normal data traffic. The IEEE1500 Char fields used to directly control eye scan and symbol response extraction are ES, ESWORD, ES BIT SELECT, ESLEN, ESPO, ESVO, ESVO OVR, ESRUN and ESDONE, see Table 23. Eye scan errors are accumulated in ECOUNT.

The required eyescan mode is selected via the ES field, as shown in Table 24. When enabled, only data from the bit position within the 20-bit word specified via ES BIT SELECT is analyzed. In other words, only eye scan errors associated with data output at this bit position will accumulate in ECOUNT. The maximum legal ES BIT SELECT is 10011.

When ES[3] = 0, the selected analysis runs continuously. However, when ES[3] = 1, only the number of qualified samples specified by ESLEN, as shown in Table 25. In this case, analysis is started by writing a 1 to ESRUN (it is not necessary to set it back to 0). When analysis completes, ESDONE will be set to 1.

When ESVO OVR = 1, the ESVO field determines the amount of offset voltage that is applied to the eye scan data samplers associated with rxpi and rxni. The amount of offset is variable between 0 and 300mV in increments of ~10mV, as shown in Table 26. When ES[3] = 1, ESVO OVR must be 0 to allow the optimized voltage offset to be read back via ESVO.

The phase position of the samplers associated with rxpi and rxni, is controlled to a precision of 1/32UI. When ES is not 00, the phase position can be adjusted forwards or backwards by more than one UI using the ESPO field, as shown in Table 27. In normal use, the range should be limited to ±0.5UI (+15 to –16 phase steps).

7.3.22 JESD204B Pattern Test

The DAC37J82/DAC38J82 supports the following test patterns for JESD204B:

• Link layer test pattern
  • Verify repeating /D.21.5/ high frequency pattern for random jitter (RJ)
  • Verify repeating /K.28.5/ mixed frequency pattern for deterministic jitter (DJ)
  • Verify repeating initial lane alignment (ILA) sequence
  • RPAT, JSPAT or JTSPAT pattern can be verified using errors counter of 8b/10b errors produced over an amount of time to get an estimate of BER.
• Transport layer test pattern: implements a short transport layer pattern check based on F = 1,2,4 or 8. The short test pattern has a duration of one frame period and is repeated continuously for the duration of the test. Refer to JESD204B standard section 5.1.6 for more details.
  • F = 1 : Looks for a constant 0xF1.
  • F = 2 : Each frame should consist of 0xF1, 0xE2
  • F = 4 : Looks for a constant 0xF1, 0xE2, 0xD3, 0xC4
  • F = 8 : Each frame should consist of 0xF1, 0xE2, 0xD3, 0xC4, 0xB5, 0xA6, 0x97, 0x81

Users can select to output the internal data (ex, the 8b/10 decoder output, comma alignment output, lane alignment output, frame alignment output, descrambler output, etc ) of a JESD link for test purpose. See jesd_testbus_sel for configuration details.

7.3.23 Temperature Sensor

The DAC37J82/DAC38J82 incorporates a temperature sensor block which monitors the temperature by measuring the voltage across 2 transistors. The voltage is converted to an 8-bit digital word using a successive-approximation (SAR) analog to digital conversion process. The result is scaled, limited and formatted as a twos complement value representing the temperature in degrees Celsius.

The sampling is controlled by the serial interface signals SDENB and SCLK. If the temperature sensor is enabled (tsense_sleep = “0” in register config26) a conversion takes place each time the serial port is written or read. The data is only read and sent out by the digital block when the temperature sensor is read in memin_tempdata in config7. The conversion uses the first eight clocks of the serial clock as the capture and conversion clock, the data is valid on the falling eighth SCLK. The data is then clocked out of the chip on the rising edge of the ninth SCLK. No other clocks to the chip are necessary for the temperature sensor operation. As a result the temperature sensor is enabled even when the device is in sleep mode.

In order for the process described above to operate properly, the serial port read from config6 must be done with an SCLK period of at least 1 μs. If this is not satisfied the temperature sensor accuracy is greatly reduced.

7.3.24 Alarm Monitoring

The DAC37J82/DAC38J82 includes a flexible set of alarm monitoring that can be used to alert of a possible malfunction scenario. All the alarm events can be accessed either through the SIP registers and/or through the ALARM pin. Once an alarm is set, the corresponding alarm bit in register configtbd must be reset through the serial interface to allow further testing. The set of alarms includes the following conditions:

• JESD alarms
  • multiframe alignment_error. Occurs when multiframe alignment fails.
  • frame alignment error. Occurs when multiframe alignment fails.
  • link configuration error. Occurs when there is wrong link configuration.
  • elastic buffer overflow. Occurs when bad RBD value is used.
  • elastic buffer match error. Occurs when the first non-/K/ doesn’t match the programmed data.
  • code synchronization error.
  • 8b/10b not-in-table decode error.
  • 8b/10 disparity error.
  • alarm_from_shorttest. Occurs when fails the short pattern test.
• SerDes alarms
  • memin_rw_losdct. Occurs when there are loss of signal detect from SerDes lanes.
  • FIFO write error. Occurs if write request and FIFO is full.
  • FIFO write full: Occurs if FIFO is full.
  • FIFO read error. Occurs if read request and FIFO is empty.
  • FIFO read empty: Occurs if FIFO is empty.
  • alarm_rw0_pll. Occurs if the PLL in the SerDes block R0 goes out of clock.
  • alarm_rw1_pll. Occurs if the PLL in the SerDes block R0 goes out of clock.
• SYSREF alarm
  • alarm_sysref_err. Occurs when the SYSREF is received at an unexpected time. If too many of these occur it will cause the JESD to go into synchronization mode again.
• DAC PLL alarm
  • alarm_from_pll. Occurs when the DAC PLL is out of lock.
• PAP alarms
  • alarm_pap. Occurs when the average power is above the threshold. While any alarm_pap is asserted the attenuation for the appropriate data path is applied.

7.3.25 LVPECL Inputs

Figure 75 shows an equivalent circuit for the DAC input clock (DACCLKP/N) and the SYSREF (SYSREFP/N).

7.3.26 CMOS Digital Inputs

Figure 76 shows a schematic of the equivalent CMOS digital inputs of the DAC37J82/DAC38J82. SDIO, SCLK, TCLK, SLEEP, TESTMODE and TXENABLE have pull-down resistors while SDENB, RESETB, TMS, TDI and TRSTB have pull-up resistors internal to the DAC37J82/DAC38J82. See the specification table for logic thresholds. The pull-up and pull-down circuitry is approximately equivalent to 100kΩ.

7.3.27 Reference Operation

The DAC37J82/DAC38J82 uses a bandgap reference and control amplifier for biasing the full-scale output current. The full-scale output current is set by applying an external resistor R_BIAS to pin BIASJ. The bias current I_BIAS through resistor R_BIAS is defined by the on-chip bandgap reference voltage and control amplifier. The default full-scale output current equals 64 times this bias current and can thus be expressed as:

IOUT_FS = 16 x I_BIAS = 64 x V_EXTIO / R_BIAS

The DAC37J82/DAC38J82 has a 4-bit coarse gain control coarse_dac(3:0) in the configtbd register. Using gain control, the IOUT_FS can be expressed as:

IOUT_FS = (coarse_dac + 1) /16 x I_BIAS x 64 = (coarse_dac + 1) /16 x V_EXTIO / R_BIAS x 64

where V_EXTIO is the voltage at pin EXTIO. The bandgap reference voltage delivers an accurate voltage of 0.9V. This reference is active when extref_ena = ‘0’ in configtbd. An external decoupling capacitor C_EXT of 0.1 µF should be connected externally to pin EXTIO for compensation. The bandgap reference can additionally be used for external reference operation. In that case, an external buffer with high impedance input should be applied in order to limit the bandgap load current to a maximum of 100 nA. The internal reference can be disabled and overridden by an external reference by setting the extref_ena control bit. Capacitor C_EXT may hence be omitted. Pin EXTIO thus serves as either input or output node.

The full-scale output current can be adjusted from 30 mA down to 10 mA by varying resistor R_BIAS or changing the externally applied reference voltage.

7.3.28 Analog Outputs

The CMOS DACs consist of a segmented array of PMOS current sources, capable of sourcing a full-scale output current up to 30 mA. Differential current switches direct the current to either one of the complimentary output nodes IOUTP or IOUTN. Complimentary output currents enable differential operation, thus canceling out common mode noise sources (digital feed-through, on-chip and PCB noise), dc offsets, even order distortion components, and increasing signal output power by a factor of four.

The full-scale output current is set using external resistor R_BIAS in combination with an on-chip bandgap voltage reference source (+0.9 V) and control amplifier. Current I_BIAS through resistor R_BIAS is mirrored internally to provide a maximum full-scale output current equal to 16 times I_BIAS.

The relation between IOUTP and IOUTN can be expressed as:

IOUT_FS = IOUTP + IOUTN

We will denote current flowing into a node as –current and current flowing out of a node as +current. Since the output stage is a current source the current flows from the IOUTP and IOUTN pins. The output current flow in each pin driving a resistive load can be expressed as:

IOUTP = IOUT_FS x CODE / 65536

IOUTN = IOUT_FS x (65535 – CODE) / 65536

where CODE is the decimal representation of the DAC data input word.

For the case where IOUTP and IOUTN drive resistor loads R_L directly, this translates into single ended voltages at IOUTP and IOUTN:

VOUTP = IOUT1 x R_L

VOUTN = IOUT2 x R_L

Assuming that the data is full scale (65535 in offset binary notation) and the R_L is 25 Ω, the differential voltage between pins IOUTP and IOUTN can be expressed as:

VOUTP = 20mA x 25 Ω = 0.5 V

VOUTN = 0mA x 25 Ω = 0 V

VDIFF = VOUTP – VOUTN = 0.5V

Note that care should be taken not to exceed the compliance voltages at node IOUTP and IOUTN, which would lead to increased signal distortion.

7.3.29 DAC Transfer Function

The DAC37J82/DAC38J82 can be easily configured to drive a doubly terminated 50 Ω cable using a properly selected RF transformer. Figure 77 and Figure 78 show the 50 Ω doubly terminated transformer configuration with 1:1 and 4:1 impedance ratio, respectively. Note that the center tap of the primary input of the transformer has to be grounded to enable a DC current flow. Applying a 20 mA full-scale output current would lead to a 0.5 Vpp for a 1:1 transformer and a 1 Vpp output for a 4:1 transformer. The low dc-impedance between IOUTP or IOUTN and the transformer center tap sets the center of the ac-signal to GND, so the 1 Vpp output for the 4:1 transformer results in an output between –0.5 V and +0.5 V.

7.4.1 Clocking Modes

The DAC37J82/DAC38J82 has a single differential clock DACCLKN/P to clock the DAC cores and internal digital logic. The DAC37J82/DAC38J82 DACCLK can be sourced directly or generated through an on-chip low-jitter phase-locked loop (PLL).

In those applications requiring extremely low noise it is recommended to bypass the PLL and source the DAC clock directly from a high-quality external clock to the DACCLK input. In most applications system clocking can be simplified by using the on-chip PLL to generate the DAC core clock while still satisfying performance requirements. In this case the DACCLK pins are used as the reference frequency input to the PLL.

7.4.2 PRBS Test Mode

The DAC37J82 and DAC38J82 support three types of PRBS sequences (2⁷-1, 2²³-1, and 2³¹-1) to verify the SerDes via SIF. To run the PRBS test on the DAC, users first need to setup the DAC for normal use, then make the following SPI writes:

1. config74, set bits 4:0 to 0x1E to disable JESD clock.
2. config61, set bits 14:12 to 0x2 to enable the 7-bit PRBS test pattern; or set bits 14:12 to 0x3 to enable the 23-bit PRBS test pattern; or set bits 14:12 to 0x4 to enable the 31-bit PRBS test pattern.
3. config27, set bits 11:8 to 0x3 to output PRBS testfail on ALARM pin.
4. config27, set bits 14:12 to the lane to be tested (0 through 7).
5. config62, make sure bits 12:11 are set to 0x0 to disable character alignment.

Users should monitor the ALARM pin to see the results of the test. If the test is failing, ALARM will be high (or toggling if marginal). If the test is passing, the ALARM will be low.

Table 30. Register Map

Name	Address	Default	(MSB) Bit 15	Bit 14	Bit 13	Bit 12	Bit 11	Bit 10	Bit 9	Bit 8	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	(LSB) Bit 0
config0	0x00	0x0218	qmc_ offsetab _ena	qmc_ offsetcd _ena	qmc _corrab _ena	qmc_ corrcd _ena	interp(3:0)				alarm_zeros _txenable _ena	outsum _ena	alarm_ zeros _jesd data_ena	alarm_out _ena	alarm _out_pol	pap _ena	inv_sinc _ab _ena	inv_sinc _cd_ena
config1	0x01	0x0003	sfrac_ ena_ab	sfrac_ ena_cd	lfrac_ ena_ab	lfrac_ ena_cd	sfrac_ sel_ab	sfrac_ sel_cd	reserved	reserved	daca_ compliment	dacb_ compliment	dacc_ compliment	dacd_ compliment	reserved	reserved	reserved	reserved
config2	0x02	0x2002	dac_bitwidth(1:0)		zer _invalid _data	shorttest _ena	reserved	reserved	reserved	reserved	sif4 _ena	mixer _ena	mixer _gain	nco _ena	reserved	reserved	twos	sif_reset
config3	0x03	0xF380	coarse_dac(3:0)				reserved				fif _error _zeros _data _ena	reserved						sif _txenable
config4	0x04	0x00FF	alarms_mask(15:0)
config5	0x05	0xFFFF	alarms_mask(31:16)
config6	0x06	0xFFFF	alarms_mask(47:32)
config7	0x07	0x0000	memin_tempdata(7:0)								reserved			memin_lane_skew(4:0)
config8	0x08	0x0000	reserved	reserved	reserved	qmc_offseta(12:0)
config9	0x09	0x0000	reserved	reserved	reserved	qmc_offsetb(12:0)
config10	0x0A	0x0000	reserved	reserved	reserved	qmc_offsetc(12:0)
config11	0x0B	0x0000	reserved	reserved	reserved	qmc_offsetd(12:0)
config12	0x0C	0x0400	reserved	reserved	reserved	reserved	reserved	qmc_gaina(10:0)
config13	0x0D	0x0400	fs8	fs4	fs2	fsm4	reserved	qmc_gainb(10:0)
config14	0x0E	0x0400	reserved	reserved	reserved	reserved	reserved	qmc_gainc(10:0)
config15	0x0F	0x0400	output _delayab _reserved(1:0)		output _delaycd _reserved(1:0)		reserved	qmc_gaind(10:0)
config16	0x10	0x0000	reserved	reserved	reserved	reserved	qmc_phaseab(11:0)
config17	0x11	0x0000	reserved	reserved	reserved	reserved	qmc_phasecd(11:0)
config18	0x12	0x0000	phaseoffsetab(15:0)
config19	0x13	0x0000	phaseoffsetcd(15:0)
config20	0x14	0x0000	phaseaddab(15:0)
config21	0x15	0x0000	phaseaddab(31:16)
config22	0x16	0x0000	phaseaddab(47:32)
config23	0x17	0x0000	phaseaddcd(15:0)
config24	0x18	0x0000	phaseaddcd(31:16)
config25	0x19	0x0000	phaseaddcd(47:32)
config26	0x1A	0x0020	reserved						reserved	vbgr _sleep	biasopamp _sleep	tsense _sleep	pll _sleep	clkrecv _sleep	daca _sleep	dacb _sleep	dacc _sleep	dacd _sleep
config27	0x1B	0x0000	extref _ena	dtest_lane(2:0)			dtest(3:0)				reserved	reserved	atest(5:0)
config28	0x1C	0x0000	reserved								reserved
config29	0x1D	0x0000	reserved								reserved
config30	0x1E	0x1111	syncsel_qmoffsetab(3:0)				syncsel_qmoffsetcd(3:0)				syncsel_qmcorrab(3:0)				syncsel_qmcorrcd(3:0)
config31	0x1F	0x1140	syncsel_mixerab(3:0)				syncsel_mixercd(3:0)				syncsel_nco(3:0)				reserved		sif_sync	reserved
config32	0x20	0x0000	syncsel_dither(3:0)				reserved				syncsel_pap(3:0)				syncsel_fir5a(3:0)
config33	0x21	0x0000	reserved
config34	0x22	0x1B1B	patha_in_sel(1:0)		pathb_in_sel(1:0)		pathc_in_sel(1:0)		pathd_in_sel(1:0)		patha_out_sel(1:0)		pathb_out_sel(1:0)		pathc_out_sel(1:0)		pathd_out_sel(1:0)
config35	0x23	0xFFFF	sleep_cntl(15:0)
config36	0x24	0x0000	reserved									cdrvser_sysref_mode(2:0)			reserved		reserved
config37	0x25	0x0000	clkjesd_div(2:0)			reserved			reserved			reserved			reserved			reserved
config38	0x26		dither_ena(3:0)				dither_mixer_ena(3:0)				dither_sra_sel3:0)				reserved		reserved	dither _zero
config39	0x27	0x0000	reserved(15:0)
config40	0x28	0x0000	reserved(15:0)
config41	0x29	0x0000	reserved(15:0)
config42	0x2A	0x0000	reserved(15:0)
config43	0x2B	0x0000	reserved(15:0)
config44	0x2C	0x0000	reserved(15:0)
config45	0x2D	0x0000	reserved	reserved											pap_ dlylen_sel	pap_gain(2:0)
config46	0x2E	0xFFFF	pap_vth(15:0)
config47	0x2F	0x0004	reserved	titest_dieid _read_ena	reserved	reserved										reserved	reserved	sifdac_ena
config48	0x30	0x0000	sifdac(15:0)
config49	0x31	0x0000	lockdet_adj(2:0)			pll_reset	pll_ndivsync_ena	pll_ena	pll_cp(1:0)		pll_n(4:0)					memin_pll_lfvolt(2:0)
config50	0x32	0x0000	pll_m(7:0)								pll_p(3:0)				reserved
config51	0x33	0x0100	pll_vcosel	pll_vco(5:0)						pll_vcoitune(1:0)		pll_cp_adj(4:0)					reserved
config52	0x34	0x0000	syncb _lvds _lopwrb	syncb _lvds _lopwra	syncb _lvds _lpsel	syncb _lvds _effuse _sel	reserved		reserved	lvds _sleep	lvds _sub_ena	reserved(6:0)
config53	0x35	0x0000	reserved				reserved				reserved				reserved
config54	0x36	0x0000	reserved
config55	0x37	0x0000	reserved
config56	0x38	0x0000	reserved
config57	0x39	0x0000	reserved
config58	0x3A	0x0000	reserved
config59	0x3B	0x0000	serdes _clk_sel	serdes_refclk_div(3:0)				reserved									reserved
config60	0x3C	0x0000	rw_cfgpll(15:0)
config61	0x3D	0x0000	reserved	rw_cfgrx0(14:0)
config62	0x3E	0x0000	rw_cfgrx0(15:0)
config63	0x3F	0x0000	reserved								INVPAIR(7:0)
config64	0x40	0x0000	reserved
config65	0x41	0x0000	errorcnt_link0(15:0)
config66	0x42	0x0000	errorcnt_link1(15:0)
config67	0x43	0x0000	errorcnt_link2(15:0)
config68	0x44	0x0000	errorcnt_link3(15:0)
config69	0x45	0x0000	reserved
config70	0x46	0x0044	lid0(4:0)					lid1(4:0)					lid2(4:0)					reserved
config71	0x47	0x190A	lid3(4:0)					lid4(4:0)					lid5(4:0)					reserved
config72	0x48	0x31C3	lid6(4:0)					lid7(4:0)					reserved		subclassv(2:0)			jesdv
config73	0x49	0x0000	link_assign(15:0)
config74	0x4A	0x001E	lane_ena(7:0)								jesd_test _seq(1:0)		dual	init_state(3:0)				jesd _reset_n
config75	0x4B	0x0000	reserved			rbd_m1(4:0)					f_m1(7:0)
config76	0x4C	0x0000	reserved			k_m1(4:0)					reserved	reserved	reserved	l_m1(4:0)
config77	0x4D	0x0300	m_m1(7:0)								reserved			s_m1(4:0)
config78	0x4E	0x0F0F	reserved			nprime_m1(4:0)					reserved	hd	scr	n_m1(4:0)
config79	0x4F	0x1CC1	match_data(7:0)								match _specific	match _ctrl	no_lane _sync	reserved				jesd _commaalign _ena
config80	0x50	0x0000	adjcnt_link0(3:0)				adjdir_link0	bid_link0(3:0)				cf_link0(4:0)					cs_link0(1:0)
config81	0x51	0x00FF	did_link0(7:0)								sync_request_ena_link0(7:0)
config82	0x52	0x00FF	reserved						disable _err_report _link0	phadj _link0	error_ena_link0(7:0)
config83	0x53	0x0000	adjcnt_link1(3:0)				adjdir_link1	bid_link1(3:0)				cf_link1(4:0)					cs_link1(1:0)
config84	0x54	0x00FF	did_link1(7:0)								sync_request_ena_link1(7:0)
config85	0x55	0x00FF	reserved						disable _err _report _link1	phadj _link1	error_ena_link1(7:0)
config86	0x56	0x0000	adjcnt_link2(3:0)				adjdir_link2	bid_link2(3:0)				cf_link2(4:0)					cs_link2(1:0)
config87	0x57	0x00FF	did_link2(7:0)								sync_request_ena_link2(7:0)
config88	0x58	0x00FF	reserved						disable _err _report _link2	phadj _link2	error_ena_link2(7:0)
config89	0x59	0x0000	adjcnt_link3(3:0)				adjdir_link3	bid_link3(3:0)				cf_link3(4:0)					cs_link3(1:0)
config90	0x5A	0x00FF	did_link3(7:0)								sync_request_ena_link3(7:0)
config91	0x5B	0x00FF	reserved						disable _err _report _link3	phadj _link3	error_ena_link3(7:0)
config92	0x5C	0x1111	err_cnt _clr_link3	sysref_mode_link3(2:0)			err_cnt _clr_link2	sysref_mode_link2(2:0)			err_cnt _clr_link1	sysref_mode_link1(2:0)			err_cnt _clr_link0	sysref_mode_link0(2:0)
config93	0x5D	0x0000	reserved
config94	0x5E	0x0000	res1(7:0)								res2(7:0)
config95	0x60	0x0123	reserved	octetpath_sel(0)(2:0)			reserved	octetpath_sel(1)(2:0)			reserved	octetpath_sel(2)(2:0)			reserved	octetpath_sel(3)(2:0)
config96	0x61	0x0456	reserved	octetpath_sel(4)(2:0)			reserved	octetpath_sel(5)(2:0)			reserved	octetpath_sel(6)(2:0)			reserved	octetpath_sel(7)(2:0)
config97	0x62	0x000F	syncn_pol	reserved			syncncd_sel(3:0)				syncnab_sel(3:0)				syncn_sel(3:0)
config98	0x63	0x0000	reserved	reserved			reserved				reserved
config98	0x64	0x0000	reserved	reserved			reserved				reserved				Reserved
config100	0x65	0x0000	alarm_l_error(0)(7:0)								reserved				alarm_fifo_flags(0)(3:0)
config101	0x66	0x0000	alarm_l_error(1)(7:0)								reserved				alarm_fifo_flags(1)(3:0)
config102	0x67	0x0000	alarm_l_error(2)(7:0)								reserved				alarm_fifo_flags(2)(3:0)
config103	0x68	0x0000	alarm_l_error(3)(7:0)								reserved				alarm_fifo_flags(3)(3:0)
config104	0x69	0x0000	alarm_l_error(4)(7:0)								reserved				alarm_fifo_flags(4)(3:0)
config105	0x6A	0x0000	alarm_l_error(5)(7:0)								reserved				alarm_fifo_flags(5)(3:0)
config106	0x6B	0x0000	alarm_l_error(6)(7:0)								reserved				alarm_fifo_flags(6)(3:0)
config107	0x6C	0x0000	alarm_l_error(7)(7:0)								reserved				alarm_fifo_flags(7)(3:0)
config108	0x6D	0x0000	alarm_sysref_err(3:0)				alarm_pap(3:0)				reserved				alarm_rw0 _pll	alarm_rw1 _pll	reserved	alarm_from _pll
config109	0x6E	0x00xx	alarm_from_shorttest(7:0)								memin_rw_losdct(7:0)
config110	0x6F	0x0000	sfrac_coef0_ab(1;0)		sfrac_coef1_ab(4;0)					sfrac_coef2_ab(7;0)								Reserved
config111	0x70	0x0000	reserved						sfrac_coef3_ab(9;0)
config112	0x71	0x0000	sfrac_coef4_ab(15;0)
config113	0x72	0x0000	sfrac_coef4_ab(18:16)			reserved			sfrac_coef5_ab(9;0)
config114	0x73	0x0000	reserved							sfrac_coef6_ab(8;0)
config115	0x74	0x0000	sfrac_coef7_ab(6;0)							sfrac_coef8_ab(4;0)					sfrac_coef9_ab(1;0)		Reserved
config116	0x75	0x0000	sfrac_invgain_ab(15:0)
config117	0x76	0x0000	sfrac_invgain_ab(19:16)				reserved						lfras_coefsel_a(2:0)			lfras_coefsel_b(2:0)
config118	0x77	0x0000	sfrac_coef0_cd(1;0)		sfrac_coef1_cd(4;0)					sfrac_coef2_cd7;0)								Reserved
config119	0x78	0x0000	reserved						sfrac_coef3_cd(9;0)
config120	0x79	0x0000	sfrac_coef4_cd(15;0)
config121	0x7A	0x0000	sfrac_coef4_cd(18:16)			reserved			sfrac_coef5_cd(9;0)
config122	0x7B	0x0000	reserved							sfrac_coef6_cd(8;0)
config123	0x7C	0x0000	sfrac_coef7_cd(6;0)							sfrac_coef8_cd(4;0)					sfrac_coef9_cd(1;0)		Reserved
config124	0x7D	0x0000	sfrac_invgain_cd(15:0)
config125	0x7E	0x0000	sfrac_invgain_cd(19:16)				reserved						lfras_coefsel_c(2:0)			lfras_coefsel_d(2:0)
config126	0x7F	0x0000	reserved				reserved				reserved				reserved
config127	0x80	0x0000	memin _efc _autoload _done	memin_efc_error(4:0)					reserved		reserved			vendorid(1:0)		versionid(2:0)

7.5.1 Register Descriptions

Addresses config100 – config107 are dual purpose registers. When config47(14) is set to a ‘1’ then config100 – config107 become the DIEID(127:0). Normal function (config47(14)=’0’) is shown below.