ZHCSCG7B January   2014  – May 2014 DAC37J82 , DAC38J82

PRODUCTION DATA.  

1. 1 特性
2. 2 应用范围
3. 3 说明
4. 4 修订历史记录
5. 5 Pin Configuration and Functions
6. 6 Specifications
   1. 6.1  Absolute Maximum Ratings
   2. 6.2  Handling Ratings
   3. 6.3  Recommended Operating Conditions
   4. 6.4  Thermal Information
   5. 6.5  DC Electrical Characteristics
   6. 6.6  Digital Electrical Characteristics
   7. 6.7  AC Electrical Characteristics
   8. 6.8  Timing Requirements
   9. 6.9  Switching Characteristics
   10. 6.10 Typical Characteristics
7. 7 Detailed Description
   1. 7.1 Overview
   2. 7.2 Functional Block Diagram
   3. 7.3 Feature Description
      1. 7.3.1  Serdes Input
      2. 7.3.2  Serdes Rate
      3. 7.3.3  Serdes PLL
      4. 7.3.4  Serdes Equalizer
      5. 7.3.5  JESD204B Descrambler
      6. 7.3.6  JESD204B Frame Assembly
      7. 7.3.7  Serial Peripheral Interface (SPI)
      8. 7.3.8  Multi-Device Synchronization
      9. 7.3.9  Input Multiplexer
      10. 7.3.10 FIR Filters
      11. 7.3.11 Full Complex Mixer
      12. 7.3.12 Coarse Mixer
      13. 7.3.13 Dithering
      14. 7.3.14 Complex Summation
      15. 7.3.15 Quadrature Modulation Correction (QMC)
          1. 7.3.15.1 Gain and Phase Correction
          2. 7.3.15.2 Offset Correction
      16. 7.3.16 Group Delay Correction Block
          1. 7.3.16.1 Fine Fractional Delay FIR Filter
          2. 7.3.16.2 Coarse Fractional Delay FIR Filter
      17. 7.3.17 Output Multiplexer
      18. 7.3.18 Power Measurement And Power Amplifier Protection
      19. 7.3.19 Serdes Test Modes
      20. 7.3.20 Error Counter
      21. 7.3.21 Eye Scan
      22. 7.3.22 JESD204B Pattern Test
      23. 7.3.23 Temperature Sensor
      24. 7.3.24 Alarm Monitoring
      25. 7.3.25 LVPECL Inputs
      26. 7.3.26 CMOS Digital Inputs
      27. 7.3.27 Reference Operation
      28. 7.3.28 Analog Outputs
      29. 7.3.29 DAC Transfer Function
   4. 7.4 Device Functional Modes
      1. 7.4.1 Clocking Modes
         1. 7.4.1.1 PLL Bypass Mode
         2. 7.4.1.2 PLL Mode
      2. 7.4.2 PRBS Test Mode
   5. 7.5 Register Map
      1. 7.5.1 Register Descriptions
8. 8 Applications and Implementation
   1. 8.1 Application Information
   2. 8.2 Typical Applications
      1. 8.2.1 Low-IF Wideband LTE Transmitter
         1. 8.2.1.1 Design Requirements
         2. 8.2.1.2 Detailed Design Procedure
            1. 8.2.1.2.1 Data Input Rate
            2. 8.2.1.2.2 Intermediate Frequency
            3. 8.2.1.2.3 Interpolation
            4. 8.2.1.2.4 DAC PLL Setup
            5. 8.2.1.2.5 Serdes Lanes
         3. 8.2.1.3 Application Performance Plots
      2. 8.2.2 Zero-IF Wideband Transmitter
         1. 8.2.2.1 Design Requirements
         2. 8.2.2.2 Detailed Design Procedure
            1. 8.2.2.2.1 Data Input Rate
            2. 8.2.2.2.2 Interpolation
            3. 8.2.2.2.3 Serdes Lanes
            4. 8.2.2.2.4 LO Feedthrough and Sideband Correction
         3. 8.2.2.3 Application Performance Plots
   3. 8.3 Initialization Set Up
9. 9 Power Supply Recommendations
10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
11. 11器件和文档支持
    1. 11.1 相关链接
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 术语表
12. 12机械封装和可订购信息