9.2.4 Calculating valid JESD204B SYSREF Frequency

Valid SYSREF frequencies depend on the following parameters:

1. Sample clock frequency
2. JESD204B internal clock divider value (CLKJESD_DIV). This depends on the DAC JESD204B L-M-F-S mode and interpolation
3. Number of octets in a frame (F)
4. Number of frames in a multi-frame (K)

Maximum SYSREF frequency = (Sample clock frequency/N),

where N =LCM(CLKJESD_DIV,4 x K x F). N is the Least common multiple of 4 x K x F and CLKJESD_DIV.

All valid SYSREF frequencies are integer divisors of the maximum SYSREF frequency.

Example:

Given sampling clock frequency = 4.9152 GSPS, interpolation =2, DAC Mode=L-M-F-S=4-1-1-2 and K=20:

CLKJESD_DIV = 8 (CLKJESD_DIV)

Maximum SYSREF Frequency = 4915.2 MHz/80 = 61.44 MHz

Valid SYSREF Frequencies = 61.44 MHz/n, where n is any positive integer.