8.3.1 Stability Circuit

For a current-to-voltage design (see Figure 20), the DAC8811 current output (I_OUT) and the connection with the inverting node of the op amp should be as short as possible and according to correct PCB layout design. For each code change, there is a step function. If the GBP of the op amp is limited and parasitic capacitance is excessive at the inverting node then gain peaking is possible. Therefore, for circuit stability, a compensation capacitor C1 (4 pF to 20 pF typ) can be added to the design, as shown in Figure 20.

Figure 20. Gain Peaking Prevention Circuit With Compensation Capacitor

8.3.2 Positive Voltage Output Circuit

As Figure 21 illustrates, in order to generate a positive voltage output, a negative reference is input to the DAC8811. This design is suggested instead of using an inverting amp to invert the output due to tolerance errors of the resistor. For a negative reference, V_OUT and GND of the reference are level-shifted to a virtual ground and a –2.5 V input to the DAC8811 with an op amp.

Figure 21. Positive Voltage Output Circuit

8.3.3 Bipolar Output Circuit

The DAC8811, as a 2-quadrant multiplying DAC, can be used to generate a unipolar output. The polarity of the full-scale output I_OUT is the inverse of the input reference voltage at V_REF.

Some applications require full 4-quadrant multiplying capabilities or bipolar output swing. As shown in Figure 22, external op amp U4 is added as a summing amp and has a gain of 2X that widens the output span to 5 V. A 4-quadrant multiplying circuit is implemented by using a 2.5-V offset of the reference voltage to bias U4. According to the circuit transfer equation given in Equation 2, input data (D) from code 0 to full scale produces output voltages of V_OUT = -2.5 V to V_OUT = +2.5 V.

Equation 2.

External resistance mismatching is the significant error in Figure 22.

Figure 22. Bipolar Output Circuit

8.3.4 Programmable Current Source Circuit

A DAC8811 can be integrated into the circuit in Figure 23 to implement an improved Howland current pump for precise voltage to current conversions. Bidirectional current flow and high voltage compliance are two features of the circuit. With a matched resistor network, the load current of the circuit is shown by Equation 3:

Equation 3.

The value of R3 in the previous equation can be reduced to increase the output current drive of U3. U3 can drive ±20 mA in both directions with voltage compliance limited up to 15 V by the U3 voltage supply. Elimination of the circuit compensation capacitor C1 in the circuit is not suggested as a result of the change in the output impedance Z_O, according to Equation 4:

Equation 4.

As shown in Equation 4, with matched resistors, Z_O is infinite and the circuit is optimum for use as a current source. However, if unmatched resistors are used, Z_O is positive or negative with negative output impedance being a potential cause of oscillation. Therefore, by incorporating C1 into the circuit, possible oscillation problems are eliminated. The value of C1 can be determined for critical applications; for most applications, however, a value of several pF is suggested.

Figure 23. Programmable Bidirectional Current Source Circuit

Table 1. Control Logic Truth Table⁽¹⁾

8.5.1 DAC8811 Input Shift Register

The DAC8811 has a 3-wire serial interface (CS, SCLK, and DIN) compatible with SPI, QSPI, and Microwire interface standards, as well as most DSPs. See Figure 1 for an example of a typical write sequence.

The input shift register is 16 bits wide, as shown in Figure 25. The write sequence begins by bringing the CS line low. Data from the DIN line are clocked into the 16-bit shift register on each rising edge of CLK. The serial clock frequency can be as high as 50 MHz, making the DAC8811 compatible with high-speed DSPs. On the 16^th rising edge of the serial clock, the last data bit is clocked in and the programmed function is executed.

At this point, the CS line may be kept low or brought high. In either case, it must be brought high for a minimum of 20 ns before the next write sequence so that a falling edge of CS can initiate the next write sequence.

Figure 25. CS Interrupt Facility