1 Features

• Single-Chip Solution to Directly Measure 64 Low-Level Currents
• Proven High-Precision, True Integrating Architecture With 100% Charge Collection
• Easy Upgrade for Existing DDC Family Applications
• Very Low Power: 3 mW/channel
• Extremely Linear:
  INL = ±0.025% of Reading ±1 ppm of FSR
• Low Noise: 6.3 ppm of FSR
• Adjustable Full-Scale Range
• Adjustable Speed
  • Data Rates up to 6 kSPS With 20-bit Performance
  • Integration Times as low as 160 µs
• Daisy-Chainable Serial Interface
• In-Package Bypass Capacitors Simplify PCB Design

2 Applications

• CT Scanner DAS
• Photodiode Sensors
• X-Ray Detection Systems

SPACER

SPACER

Simplified Schematic



Protected by US Patent #5841310

3 Description

The DDC264 is a 20-bit, 64-channel, current-input analog-to-digital (A/D) converter. It combines both current-to-voltage and A/D conversion so that 64 separate low-level current output devices, such as photodiodes, can be directly connected to its inputs and digitized.

For each of the 64 inputs, the DDC264 uses the proven dual switched integrator front-end. This configuration allows for continuous current integration: while one integrator is being digitized by the onboard A/D converter, the other is integrating the input current. This architecture provides both a very stable offset and a loss-less collection of the input current. Adjustable integration times range from 160 µs to 1 s, allowing currents from fAs to µAs to be continuously measured with outstanding precision.

The DDC264 has a serial interface designed for daisy-chaining in multi-device systems. Simply connect the output of one device to the input of the next to create the chain. Common clocking feeds all the devices in the chain so that the digital overhead in a multi-DDC264 system is minimal.

The DDC264 uses a 5-V analog supply and a 2.7-V to 3.6-V digital supply. Bypass capacitors within the DDC264 package help minimize the external component requirements. Operating over the temperature range of 0°C to 70°C, the DDC264
100-pin NFBGA package is offered in two versions: the DDC264C for low-power applications, and the DDC264CK when higher speeds are required.

1. For all available packages, see the orderable addendum at the end of the data sheet.

4 Revision History

Changes from C Revision (July 2011) to D Revision

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo
• Moved AVDD and DVDD rows to Recommended Operating Conditions tableGo
• Moved Dynamic Characteristics rows to Recommended Operating Conditions table Go
• Deleted Voltage row from Electrical Characteristics table Go
• Changed 1.65 mA to 825 µA in Voltage Reference sectionGo
• Changed 680 µA to 340 µA in Voltage Reference sectionGo
• Changed 64 to 128 in the formula in Reading the Measurement sectionGo
• Changed high-impedance to low-impedance in Shielding Analog Signal Paths sectionGo

Changes from B Revision (January, 2011) to C Revision

• Updated NOISE vs C_SENSOR table; revised values for Range 0 performance in fC and ElectronsGo

Changes from A Revision (January, 2011) to B Revision

• Changed second paragraph of Basic Integration Cycle section to correct CONV timing description errorGo