9.3.1 RESET Operation

The DIX4192-Q1 includes an asynchronous active low reset input, RST (pin 24), which may be used to initialize the internal logic at any time. The reset sequence forces all registers and buffers to their default settings. The reset low pulse duration must be a minimum of 500 ns in length. The user must not attempt a write or read operation using either the SPI or I²C port for at least 500 μs after the rising edge of RST. See Figure 6 for the reset timing sequence of the DIX4192-Q1.

In addition to reset input, the RESET bit in control register 0x01 may be used to force an internal reset, whereby all registers and buffers are forced to their default settings. Refer to Control Registers for details regarding the RESET bit function.

Upon reset initialization, all functional blocks of the DIX4192-Q1 default to the power-down state, with the exception of the SPI or I²C host interface and the corresponding control registers. The user may then program the DIX4192-Q1 to the desired configuration, and release the desired function blocks from the power-down state using the corresponding bits in control register 0x01.

Figure 6. Reset Sequence Timing

9.3.2 Master and Reference Clocks

The DIX4192-Q1 includes two clock inputs, MCLK (pin 25) and RXCKI (pin 13). The MCLK clock input is typically used as the master clock source for the audio serial ports and/or the DIT. The MCLK may also be used as the reference clock for the DIR. The RXCKI clock input is typically used for the DIR reference clock source, although it may also be used as the master or reference clock source for the audio serial ports.

In addition to the MCLK and RXCKI clock sources, the DIR core recovers a master clock from the AES3-encoded input data stream. This clock is suitable for use as a master or system clock source in many applications. The recovered master clock output, RXCKO (pin 12), may be used as the master or reference clock source for the audio serial ports and the DIT, as well as external audio devices.

The master clock frequency for the audio serial ports (Port A and Port B) depends on the Slave or Master mode configuration of the port. In Slave mode, the ports do not require a master clock because the left/right word and bit clocks are inputs, sourced from an external audio device serving as the serial bus timing master. In Master mode, the serial ports derive the left/right word and bit clock outputs from the selected master clock source, MCLK, RXCKI, or RXCKO. The left/right word clock rate is derived from the selected master clock source using one of four clock divider settings (divide by 128, 256, 384, or 512). Refer to Audio Serial Port Operation for additional details.

The DIT always requires a master clock source, which may be either the MCLK input, or the DIR recovered clock output, RXCKO. Like the audio serial ports, the DIT output frame rate is derived from the selected master clock using one of four clock divider settings (divide-by-128, -256, -384, or -512). Refer to Digital Interface Transmitter (DIT) Operation for additional details.

The DIR reference clock may be any frequency that meets the PLL1 set-up requirements, described in Control Registers. Typically, a common audio system clock rate, such as 11.2896 MHz, 12.288 MHz, 22.5792 MHz, or 24.576 MHz, may be used for this clock.

TI recommends that the clock sources for MCLK and RXCKI input be generated by low-jitter crystal oscillators for optimal performance. In general, phase-locked loop (PLL) clock synthesizers must be avoided, unless they are designed or specified for low clock jitter.

9.3.3 Audio Serial Port Operation

The DIX4192-Q1 includes two audio serial ports, Port A and Port B. Both ports are 4-wire synchronous serial interfaces, supporting simultaneous input and output operation. Because each port has only one pair of left or right word and bit clocks, the input and output sampling rates are identical. A simplified block diagram is shown in Figure 7.

The audio serial ports may be operated at sampling rates up to 216 kHz, and support audio data word lengths up to 24 bits. Philips I²S, Left-Justified, and Right-Justified serial data formats are supported. Refer to Figure 8.

The left or right word clock (LRCKA or LRCKB) and the bit clock (BCKA or BCKB) may be configured for either Master or Slave mode operation. In Master mode, these clocks are outputs, derived from the selected master clock source using internal clock dividers. The master clock source may be 128, 256, 384, or 512 times the audio input/output sampling rate, with the clock divider being selected using control register bits for each port. In Slave mode the left or right word and bit clocks are inputs, and are sourced from an external audio device acting as the serial bus master.

The LRCKA or LRCKB clocks operate at the input and output sampling rate, f_S. The BCKA and BCKB clock rates are fixed at 64 times the left or right word clock rate in Master mode. For Slave mode, the minimum BCKA and BCKB clock rate is determined by the audio data word length multiplied by two, because there are two audio data channels per left or right word clock period. For example, if the audio data word length is 24 bits, the bit clock rate must be at least 48 times the left or right word clock rate, allowing one bit clock period for each data bit in the serial bit stream.

Serial audio data is clocked into the port on the rising edge of the bit clock, while data is clocked out of the port on the falling edge of the bit clock. Refer to the Audio Serial Ports section of the Electrical Characteristics table for parametric information and Figure 1 for a timing diagram related to audio serial port operation.

The audio serial ports are configured using control registers 0x03 through 0x06. Refer to Control Registers for descriptions of the control register bits.

Figure 7. Audio Serial Port Block Diagram

Figure 8. Audio Data Formats

9.3.4 Overview of the AES3 Digital Audio Interface Protocol

This section introduces the basics of digital audio interface protocols pertaining to the transmitter (DIT) and receiver (DIR) blocks of the DIX4192-Q1. Emphasis is placed upon defining the basic terminology and characteristics associated with the AES3-2003 standard protocol, the principles of which may also be applied to a number of consumer-interface variations, including S/PDIF, IEC-60958, and EIAJ CP-1201. It is assumed that the reader is familiar with the AES3 and S/PDIF interface formats. Additional information is available from the sources listed in the 开发支持 section.

The AES3-2003 standard defines a technique for two-channel linear PCM data transmission over 110-Ω shielded twisted-pair cable. The AES-3id document extends the AES3 interface to applications employing 75-Ω coaxial cable connections. In addition, consumer transmission variants, such as those defined by the S/PDIF, IEC 60958, and CP-1201 standards, use the same encoding techniques but with different physical interfaces or transmission media. Channel status data definitions also vary between professional and consumer interface implementations.

For AES3 transmission, data is encoded into frames, with each frame containing two subframes of audio and status data, corresponding to audio Channels 1 and 2 (or Left and Right, respectively, for stereophonic audio). Figure 9 shows the AES3 frame and subframe formatting. Each subframe includes four bits for the preamble, up to 24 bits for audio and/or auxiliary data, one bit indicating data validity (V), one bit for channel status data (C), one bit for user data (U), and one bit for setting parity (P).

The 4-bit preamble is used for synchronization and identification of blocks and subframes. The X and Y preamble codes are used to identify the start of the Channel 1 and Channel 2 subframes, as shown in Figure 9. However, the X preamble for the first subframe of every 192 frames is replaced by the Z preamble, which identifies the start of a new block of channel status and user data.

Figure 9. AES3 Frame and Subframe Encoding

One block is comprised of 192 frames of data. This format translates to 192 bits each for channel status and user data for each channel. The 192 bits are organized into 24 data bytes, which are defined by the AES3-2003 and consumer standards documents. The AES18 standard defines recommended usage and formatting of the user data bits, while consumer applications may use the user data for other purposes. The DIX4192-Q1 also includes block-sized transmitter and receiver channel status and user data buffers, which have 24 bytes each for the channel status and user data assigned to audio Channels 1 and 2. Refer to Channel Status and User Data Buffer Maps for the organization of the buffered channel status and user data for the receiver and transmitter functions.

The audio data for Channel 1 and Channel 2 may be up to 24 bits in length, and occupies bits 4 through 27 of the corresponding subframe. Bit 4 is the LSB while bit 27 is the MSB. If only 20 bits are required for audio data, then bits 8 through 27 are used for audio data, while bits 4 though 7 are used for auxiliary data bits.

The validity (V) bit indicates whether or not the audio sample word being transmitted is suitable for digital-to-analog (D/A) conversion or further digital processing at the receiver end of the connection. If the validity bit is 0, then the audio sample is suitable for conversion or additional processing. If the validity bit is 1, then the audio sample is not suitable for conversion or additional processing.

The parity (P) bit is set to either a 0 or 1, such that bits 4 through 31 carry an even number of ones and zeros for even parity. The DIT block in the DIX4192-Q1 automatically manages the parity bit, setting it to a 0 or 1 as required. The DIR block checks the parity of bits 4 though 31 and generates a parity error if odd parity is detected.

The binary non-return to zero (NRZ) formatted audio and status source data for bits 4 through 31 of each subframe are encoded using a Biphase Mark format for transmission. This format allows for clock recovery at the receiver end, as well as making the interface insensitive to the polarity of the balanced cable connections. The preambles at the start of each subframe are encoded to intentionally violate the Biphase Mark formatting, making their detection by the receiver reliable, as well as avoiding the possibility of audio and status data imitating the preambles. Figure 10 shows the Biphase Mark and preamble encoding.

Although the AES3 standard originally defined transmission for sampling rates up to 48 kHz, the interface is capable of handling higher sampling rates, given that attention is paid to cable length and impedance matching. Equalization at the receiver may also be required, depending on the cable and matching factors. It is also possible to transmit and decode more than two channels of audio data using the AES3 or related consumer interfaces. Special encoding and compression algorithms are used to support multiple channels, including the Dolby® AC-3, DTS, MPEG-1/2, and other data reduced audio formats.

Figure 10. Biphase Mark Encoding

9.3.5 Digital Interface Transmitter (DIT) Operation

The DIT encodes a given two-channel or data-reduced audio input stream into an AES3-encoded output stream. In addition to the encoding function, the DIT includes differential line driver and CMOS-buffered output functions. The line driver is suitable for driving balanced or unbalanced line interfaces, while the CMOS-buffered output is designed to drive external logic or line drivers, as well as optical transmitter modules. Figure 11 shows the functional block diagram for the DIT.

The input of the DIT receives the audio data for Channels 1 and 2 from one of three possible sources: Port A, Port B, or the DIR. By default Port A is selected as the source. The DIT also requires a master clock source, which may be provided by either the MCLK input (pin 25) or RXCKO (the DIR recovered master clock output). A master clock divider is used to select the frame rate for the AES3-encoded output data. The TXDIV[1:0] bits in control register 0x07 are used to select divide by 128, 256, 384, or 512 operation.

Channel status and user data for Channels 1 and 2 are input to the AES3 encoder through the corresponding Transmitter Access (TA) data buffers. The TA data buffers are in turn loaded from the User Access (UA) buffers, which are programmed through the SPI or I²C host interface, or loaded from the DIR Receiver Access (RA) data buffers. The source of the channel status and user data is selected using the TXCUS[1:0] bits in control register 0x09. When the DIR is selected as the input source, the channel status and user data output from the DIT is delayed by one block in relation to the audio data.

The validity (V) bit may be programmed using one of two sources. The VALSEL bit in control register 0x09 is used to select the validity data source for the DIT block. The default source is the VALID bit in control register 0x07, which is written through the SPI or I²C host interface. The validity bit may also be transferred from the AES3 decoder output of the DIR, where the V bit for the DIT subframes tracks the decoded DIR value frame by frame.

The Parity (P) bit will always be generated by the AES3 encoder internal parity generator logic, such that bits 4 through 31 of the AES3-encoded subframe are even parity.

The AES3 encoder output is connected to the output line driver and CMOS buffer source multiplexers. As shown in Figure 11, the source multiplexers allow the line driver or buffer to be driven by the AES3-encoded data from the DIT, or by the bypass multiplexer, which is associated with the outputs of the four differential input line receivers preceding the DIR core. The bypass multiplexer allows for one of the four line receiver outputs to be routed to the line driver or buffer output, thereby providing a bypass mode of operation. Both the line driver and CMOS output buffer include output disables, set by the TXOFF and AESOFF bits in control register 0x08. When the outputs are disabled, they are forced to a low logic state.

The AES3 encoder includes an output mute function that sets all bits for both the Channel 1 and 2 audio and auxiliary data to zero. The preamble, V, U, and C bits are unaffected, while the P bit is recalculated. The mute function is controlled using the TXMUTE bit in control register 0x08.

Figure 11. Digital Interface Transmitter (DIT) Functional Block Diagram

The AES3 encoder includes a block start input/output pin, BLS (pin 35). The BLS pin may be programmed as an input or output. The input/output state of the BLS pin is programmed using the BLSM bit in control register 0x07. By default, the BLS pin is configured as an input.

As an input, the BLS pin may be used to force a block start condition, whereby the start of a new block of channel status and user data is initiated by generating a Z preamble for the next frame of data. The BLS input must be synchronized with the DIT internal SYNC clock. This clock is output on SYNC (pin 36). The SYNC clock rising edge is aligned with the start of each frame for the AES3-encoded data output by the DIT. Figure 12 shows the format required for an external block start signal, as well as indicating the format when the BLS pin is configured as an output. When the BLS pin is an output, the DIT generates the block start signal based upon the internal SYNC clock.

For details regarding DIT control and status registers, as well as channel status and user data buffers, refer to Control Registers and Channel Status and User Data Buffer Maps.

Figure 12. DIT Block Start Timing

9.3.6 Digital Interface Receiver (DIR) Operation

The DIR performs AES3 decoding and clock recovery and provides the differential line receiver functions. The lock range of the DIR includes frame and sampling rates from 20 kHz to 216 kHz. Figure 13 shows the functional block diagram for the DIR.

Four differential line receivers are used for signal conditioning the encoded input data streams. The receivers can be externally configured for either balanced or unbalanced cable interfaces, as well as interfacing with CMOS logic level inputs from optical receivers or external logic circuitry. See Figure 14 for a simplified schematic for the line receiver. External connections are discussed in Receiver Input Interfacing.

Figure 13. Digital Interface Receiver (DIR) Functional Block Diagram

Figure 14. Differential Line Receiver Circuit

The outputs of the four line receivers are connected to two 1-of-4 data selectors: the receiver input multiplexer and the bypass multiplexer. The input multiplexer selects one of the four line receiver outputs as the source for the AES3-encoded data stream to be processed by the DIR core. The bypass multiplexer is used to route a line receiver output to either the DIT line driver or CMOS-buffered outputs, thereby bypassing all other internal circuitry. The bypass function is useful for simple signal distribution and routing applications.

The DIR requires a reference clock, supplied by an external source applied at either the RXCKI (pin 13) or MCLK (pin 25) clock inputs. PLL1 multiplies the reference clock to a higher rate, which is used as the oversampling clock for the AES3 decoder. The decoder samples the AES3-encoded input stream in order to extract all of the audio and status data. The decoded data stream is sent on to a de-multiplexer, where audio and status data are separated for further processing and buffering. The pulse generator circuitry samples the encoded input data stream and generates a clock that is 16 times the frame/sampling rate (or f_S). The 16 f_S clock is then processed by PLL2, which further multiplies the clock rate and provides low-pass filtering for jitter attenuation. The available PLL2 output clock rates include 512 f_S, 256 f_S, and 128 f_S. The maximum available PLL2 output clock rate for a given input sampling rate is estimated by internal logic and made available for readback through status register 0x13.

The output of PLL2 may be divided by a factor of two, four, or eight, or simply passed through to the recovered master clock output, RXCKO (pin 12). The RXCKO clock may also be routed internally to other function blocks, where it may be further divided to create left/right word and bit clocks. The RXCKO output may be disabled and forced to a high-impedance state by means of a control register bit, allowing other tri-state buffered clocks to be tied to the same external circuit node, if required. By default, the RXCKO output (pin 12) is disabled and forced to a high-impedance state.

Figure 15 shows the frequency response of PLL2. Jitter attenuation starts at approximately 50 kHz. Peaking is nominally 1 dB, which is within the 2 dB maximum allowed by the AES3 standard. The receiver jitter tolerance plot for the DIR is shown in Figure 16, along with the required AES3 jitter tolerance template. The DIR jitter tolerance satisfies the AES3 requirements, as well as the requirements set forth by the IEC60958-3 specification. Figure 16 was captured using a full-scale 24-bit, two-channel, AES3-encoded input stream with a 48kHz frame rate.

The decoded audio data, along with the internally-generated sync clocks, may be routed to other function blocks, including Port A, Port B, and the DIT. The decoded channel status and user data are buffered in the corresponding Receiver Access (RA) data buffers, then transferred to the corresponding User Access (UA) data buffers, where it may be read back through either the SPI or I²C serial host interface. The contents of the RA buffers may also be transferred to the DIT UA data buffers; this transfer is shown in Figure 11. The channel status and user data bits may also be output serially through the general-purpose output pins, GPO[4:1]. Figure 17 shows the output format for the GPO pins when used for this purpose, along with the DIR block start (BLS) and frame synchronization (SYNC) clocks. The rising edges of the DIR SYNC clock output are aligned with the start of each frame for the received AES3 data.

The DIR includes a dedicated, active low AES3 decoder and PLL2 lock output, named LOCK (pin 11). The lock output is active only when both the AES3 decoder and PLL2 indicate a lock condition. Additional DIR status flags may be output at the general-purpose output (GPO) pins, or accessed through the status registers through the SPI or I²C host interface. Refer to General-Purpose Digital Outputs and Control Registers for additional information regarding the DIR status functions.

Figure 15. DIR Jitter Attenuation Characteristics

Figure 16. DIR Jitter Tolerance Plot

Figure 17. DIR Channel Status and User Data Serial Output Format Through the GPO Pins

9.3.7 General-Purpose Digital Outputs

The DIX4192-Q1 includes four general-purpose digital outputs, GPO1 through GPO4 (pins 26 through 29, respectively). A GPO pin may be programmed to a static high or low state. Alternatively, a GPO pin may be connected to one of 13 internal logic nodes, allowing the GPO pin to inherit the function of the selected signal. Control registers 0x1B through 0x1E are used to select the function of the GPO pins. For details regarding GPO output configuration, refer to Control Registers. Table 1 summarizes the available output options for the GPO pins.

9.3.8 Interrupt Output

The DIX4192-Q1 includes multiple internal status bits, many of which may be set to trigger an interrupt signal. The interrupt signal is output at INT (pin 23), which is an active low, open-drain output. The INT pin requires a pullup resistor to the VIO supply rail. The value of the pullup is not critical, but a 10-kΩ device must be sufficient for most applications. Figure 18 shows the interrupt output pin connection. The open-drain output allows interrupt pins from multiple DIX4192-Q1 devices to be connected in a wired OR configuration.

Figure 18. Interrupt Output Pin Connections

9.4.1 Host Interface Operation: Serial Peripheral Interface (SPI) Mode

The DIX4192-Q1 supports a 4-wire SPI port when the CPM input (pin 18) is forced low or tied to ground. The SPI port supports high-speed serial data transfers up to 40 Mbps. Register and data buffer write and read operations are supported.

The CS input (pin 19) serves as the active low chip select for the SPI port. The CS input must be forced low in order to write or read registers and data buffers. When CS is forced high, the data at the CDIN input (pin 21) is ignored, and the CDOUT output (pin 22) is forced to a high-impedance state. The CDIN input serves as the serial data input for the port; the CDOUT output serves as the serial data output.

The CCLK input (pin 20) serves as the serial data clock for both the input and output data. Data is latched at the CDIN input on the rising edge of CCLK, while data is clocked out of the CDOUT output on the falling edge of CCLK.

Figure 19 shows the SPI port protocol. Byte 0 is referred to as the command byte, where the most significant bit (or MSB) is the read/write bit. For the R/W bit, a 0 indicates a write operation, while a 1 indicates a read operation. The remaining seven bits of the command byte are used for the register address targeted by the write or read operation. Byte 1 is a don’t care byte, and may be set to all zeroes. This byte is included in order to retain protocol compatibility with earlier Texas Instruments digital audio interface and sample rate converter products, including the DIT4096, DIT4192, the SRC418x series devices, and the SRC419x series devices.

The SPI port supports write and read operations for multiple sequential register addresses through the implementation of an auto-increment mode. As shown in Figure 19, the auto-increment mode is invoked by simply holding the CS input low for multiple data bytes. The register address is automatically incremented after each data byte transferred, starting with the address specified by the command byte.

Refer to the SPI section of the Electrical Characteristics table and Figure 2 for specifications and a timing diagram that highlight the key parameters for SPI operation.

Figure 19. Serial Peripheral Interface (SPI) Protocol for the DIX4192-Q1

9.4.2 Host Interface Operation: PHILIPS I²C Mode

The DIX4192-Q1 supports a 2-wire Philips I²C bus interface when CPM (pin 18) is forced high or pulled up to the VIO supply rail. The DIX4192-Q1 functions as a Slave-only device on the bus. Standard and Fast modes of operation are supported. Standard mode supports data rates up to 100 kbps, while Fast mode supports data rates up to 400 kbps. Fast mode is downward compatible with Standard mode, and these modes are sometimes referred to as Fast/Standard, or F/S mode. The I²C Bus Specification (Version 2.1, January 2000), available from Philips Semiconductor, provides the details for the bus protocol and implementation. It is assumed that the reader is familiar with this specification. Refer to the I²C Standard and Fast Modes section of the Electrical Characteristics table and Figure 3 for specifications and a timing diagram that highlight the key parameters for I²C interface operation.

When the I²C mode is invoked, pin 20 becomes SCL (which serves as the bus clock) and pin 22 becomes SDA (which carries the bi-directional serial data for the bus). Pins 19 and 21 become A0 and A1, respectively, and function as the hardware configurable portion of the 7-bit slave address.

The DIX4192-Q1 uses a 7-bit Slave address; see Figure 20(a). Bits A2 through A6 are fixed and bits A0 and A1 are hardware programmable using pins 19 and 21, respectively. The programmable bits allow for up to four DIX4192-Q1 devices to be connected to the same bus. The slave address is followed by the Register Address Byte, which points to a specific register or data buffer location in the DIX4192-Q1 register map. The register address byte is comprised of seven bits for the address, and one bit for enabling or disabling auto-increment operation; see Figure 20(b). Auto-increment mode allows multiple sequential register locations to be written to or read back in a single operation, and is especially useful for block write and read operations.

Figure 21 shows the protocol for Standard and Fast mode Write operations. When writing a single register address, or multiple non-sequential register addresses, the single register write operation of Figure 21(a) may be used one or more times. When writing multiple sequential register addresses, the auto-increment mode of Figure 21(b) improves efficiency. The register address is automatically incremented by one for each successive byte of data transferred.

Figure 22 shows the protocol for Standard and Fast mode Read operations. The current address read operation of Figure 22(a) assumes the value of the register address from the previously executed write or read operation, and is useful for polling a register address for status changes. Figure 22(b) and Figure 22(c) show read operations for one or more random register addresses, with or without auto-increment mode enabled.

Figure 20. DIX4192-Q1 Slave Address and Register Address Byte Definitions

Figure 21. Fast and Standard Mode Write Operations

Figure 22. Fast and Standard Mode Read Operations

9.5.1 Register and Data Buffer Organization

The DIX4192-Q1 organizes the on-chip registers and data buffers into four pages. The currently active page is chosen by programming the Page Selection Register to the desired page number. The Page Selection Register is available on every register page at address 0x7F, allowing easy movement between pages. Table 2 indicates the page selection corresponding to the Page Selection Register value.

Register Page 0 contains the control registers used to configure the various function blocks within the DIX4192-Q1. In addition, status registers are provided for flag and error conditions, with many of the status bits capable of generating an interrupt signal when enabled. See Table 3 for the control and status register map.

Register Page 1 contains the digital interface receiver (or DIR) channel status and user data buffers. These buffers correspond to the data contained in the C and U bits of the previously received block of the AES3-encoded data stream. The contents of these buffers may be read through the SPI or I²C serial host interface and processed as required by the host system. See Table 35 for the DIR channel status buffer map, and Table 36 for the DIR user data buffer map.

Register Page 2 contains the digital interface transmitter (or DIT) channel status and user data buffers. These buffers correspond to the data contained in the C and U bits of the transmitted AES3-encoded data stream. The contents of these buffers may be written through the SPI or I²C serial host interface to configure the C and U bits of the transmitted AES3 data stream. The buffers may also be read for verification by the host system. See Table 37 for the DIT channel status buffer map, and Table 38 for the DIT user data buffer map.

Register Page 3 is reserved for factory test and verification purposes, and cannot be accessed without an unlock code. The unlock code remains private; the test modes disable normal operation of the device, and are not useful in customer applications.

9.5.2 Control Registers

See Table 3 for the control and status register map of the DIX4192-Q1. Register addresses 0x00 and 0x2D through 0x7E are reserved for factory or future use. All register addresses are expressed as hexadecimal numbers. The following pages provide detailed descriptions for each control and status register.

Figure 44. DIR Output Slip and Repeat (OSLIP) Behavior

9.5.3 Channel Status and User Data Buffer Maps

Table 35 through Table 38 show the buffer maps for the DIR and DIT channel status and user data buffers.

For Table 35, the channel status byte definitions are dependent on the transmission mode, either Professional or Consumer. Bit 0 of Byte 0 defines the transmission mode, 0 for Consumer mode, and 1 for Professional mode. This is applicable for Table 35 and Table 36.

For Table 37, the channel status byte definitions are dependent on the transmission mode, either Professional or Consumer. Bit 0 of Byte 0 defines the transmission mode, 0 for Consumer mode, and 1 for Professional mode. In Professional mode, Byte 23 for each channel is reserved for CRC data, which is automatically calculated and encoded by the DIT. There is no requirement to program Byte 23 for either channel in Professional mode.