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DLPS119B December 2018 – May 2022 DLP2010NIR

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机械数据 (封装 | 引脚)

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6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

		MIN	NOM	MAX	UNIT
SUPPLY VOLTAGE RANGE⁽³⁾
V_DD	Supply voltage for LVCMOS core logic Supply voltage for LPSDR low-speed interface	1.65	1.8	1.95	V
V_DDI	Supply voltage for SubLVDS receivers	1.65	1.8	1.95	V
V_OFFSET	Supply voltage for HVCMOS and micromirror electrode⁽⁴⁾	9.5	10	10.5	V
V_BIAS	Supply voltage for mirror electrode	17.5	18	18.5	V
V_RESET	Supply voltage for micromirror electrode	–14.5	–14	–13.5	V
\|V_DDI–V_DD\|	Supply voltage delta (absolute value)⁽⁵⁾			0.3	V
\|V_BIAS–V_OFFSET\|	Supply voltage delta (absolute value)⁽⁶⁾			10.5	V
\|V_BIAS–V_RESET\|	Supply voltage delta (absolute value)⁽⁷⁾			33	V
OUTPUT TERMINALS
I_OH	High-level output current at V_oh = 0.8 × V_DD			–30	mA
I_OL	Low-level output current at V_ol = 0.2 × V_DD			30	mA
CLOCK FREQUENCY
ƒ_clock	Clock frequency for low speed interface LS_CLK⁽⁸⁾	108		120	MHz
ƒ_clock	Clock frequency for high speed interface DCLK⁽⁹⁾	300		600	MHz
	Duty cycle distortion DCLK	44%		56%
SUBLVDS INTERFACE⁽⁹⁾
\|V_ID\|	SubLVDS input differential voltage (absolute value) Figure 6-8, Figure 6-9	150	250	350	mV
V_CM	Common mode voltage Figure 6-8, Figure 6-9	700	900	1100	mV
V_SUBLVDS	SubLVDS voltage Figure 6-8, Figure 6-9	575		1225	mV
Z_LINE	Line differential impedance (PWB/trace)	90	100	110	Ω
Z_IN	Internal differential termination resistance Figure 6-10	80	100	120	Ω
	100-Ω differential PCB trace	6.35		152.4	mm
LPSDR INTERFACE⁽¹⁰⁾
Z_LINE	Line differential impedance (PWB/trace)	61.2	68	74.8	Ω
ENVIRONMENTAL
T_ARRAY	Array temperature – long-term operational⁽¹¹⁾ ⁽¹²⁾ ⁽¹³⁾	0		40 to 70⁽¹¹⁾	°C
	Array temperature – short-term operational, 25 hr max⁽¹³⁾⁽¹⁴⁾	–20		-10
	Array temperature – short-term operational, 500hr max ⁽¹³⁾⁽¹⁴⁾	-10		0
	Array temperature – short-term operational, 500hr max ⁽¹³⁾⁽¹⁴⁾	70		75
T_WINDOW	Window temperature – operational⁽¹⁵⁾ ⁽¹⁷⁾			90	°C
\|T_DELTA\|	Absolute temperature difference between any point on the window edge and the ceramic test point TP1⁽¹⁶⁾			15	°C
CT_ELR	Cumulative time in elevated dew point temperature range			6	Months
ILL_UV	Illumination, wavelength < 420 nm			0.68	mW/cm²
ILL_VIS	Illumination wavelengths between 420 nm and 700 nm	Thermally limited
ILL_NIR	Illumination, wavelength 700 - 2500 nm			2000	mW/cm²
ILL_IR	Illumination, wavelength > 2500 nm			10	mW/cm²
ILL_θ	Illumination marginal ray angle⁽¹⁷⁾			55	deg

(1) Recommended Operating Conditions are applicable after the DMD is installed in the final product.

(2) The functional performance of the device specified in this datasheet is achieved when operating the device within the limits defined by the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the Recommended Operating Conditions limits.

(3) All voltage values are with respect to the ground pins (V_SS).

(4) V_OFFSET supply transients must fall within specified max voltages.

(5) To prevent excess current, the supply voltage delta |V_DDI – V_DD| must be less than specified limit.

(6) To prevent excess current, the supply voltage delta |V_BIAS – V_OFFSET| must be less than the specified limit.

(7) To prevent excess current, the supply voltage delta |V_BIAS – V_RESET| must be less than the specified limit.

(8) LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands.

(9) Refer to the SubLVDS timing requirements in Section 6.7.

(10) Refer to the LPSDR timing requirements in Section 6.7.

(11) Per Figure 6-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. Refer to Section 7.7 for a definition of micromirror landed duty cycle.

(12) Long-term is defined as the usable life of the device.

(13) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1) shown in Figure 7-1 and the package thermal resistance using Section 7.6.

(14) Short-term is the total cumulative time over the useful life of the device.

(15) Window temperature is the highest temperature on the window edge shown in Figure 7-1. The locations of thermal test points TP2 and TP3 in Figure 7-1 are intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, a test point should be added to that location.

(16) Temperature delta is the highest difference from the ceramic test point 1 (TP1) and anywhere on the window edge shown in Figure 7-1. The window test points TP2 and TP3 shown in Figure 7-1 are intended to result in the worst case delta temperature. If a particular application causes another point on the window edge to result in a larger delta temperature, that point should be used.

(17) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including Pond of Micromirrors (POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM) will contribute to thermal limitations described in this document, and may negatively affect lifetime.

Figure 6-1 Maximum Recommended Array Temperature – Derating Curve