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ZHCSL02C March 2020 – March 2023 DLP3021-Q1

PRODUCTION DATA

9.1 Power Supply Sequencing Requirements

CAUTION:

For reliable operation of the DMD, the following power supply sequencing requirements must be followed. Failure to adhere to the prescribed power up and power down procedures may affect device reliability.
The V_CC, V_REF, V_OFFSET, V_BIAS, and V_RESET power supplies have to be coordinated during power up and power down operations. Failure to meet any of the following requirements will result in a significant reduction in the DMD’s reliability and lifetime. Refer to Figure 9-1. V_SS must also be connected.

DMD Power Supply Power Up Procedure:

During power up, V_CC and V_REF must always start and settle before V_OFFSET, V_BIAS and V_RESET voltages are applied to the DMD.
During power up, V_BIAS does not have to start after V_OFFSET. However, it is a strict requirement that the delta between V_BIAS and V_OFFSET must be within ±8.75 V (refer to Note 1 for Figure 9-1).
During power up, the DMD’s LVCMOS input pins shall not be driven high until after V_CC and V_REF have settled at operating voltage.
During power up, there is no requirement for the relative timing of V_RESET with respect to V_OFFSET and V_BIAS.
Power supply slew rates during power up are flexible, provided that the transient voltage levels follow the requirements listed previously in Section 6.4 and in Figure 9-1.

DMD Power Supply Power Down Procedure

V_CC and V_REF must be supplied until after V_BIAS, V_RESET, and V_OFFSET are discharged to within 4 V of ground.
During power down it is not mandatory to stop driving V_BIAS prior to V_OFFSET, but it is a strict requirement that the delta between V_BIAS and V_OFFSET must be within ±8.75 V (refer to Note 1 for Figure 9-1).
During power down, the DMD’s LVCMOS input pins must be less than V_REF + 0.3 V.
During power down, there is no requirement for the relative timing of V_RESET with respect to V_OFFSET and V_BIAS.
Power supply slew rates during power down are flexible, provided that the transient voltage levels follow the requirements listed previously in Section 6.4 and in Figure 9-1.