The power-down sequence is the reverse order of the previous power-up sequence. During the power-down sequence, VDD and VDDI must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to within 4 V of ground.
During the power-down sequence, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be within the specified limit shown in Section 6.4.
During the power-down sequence, there is no requirement for the relative timing of VRESET with respect to VBIAS and VOFFSET.
Power supply slew rates during the power-down sequence, are flexible, provided that the transient voltage levels follow the requirements specified in Section 6.1, inSection 6.4, and in Section 9.3.
During the power-down sequence, LPSDR input pins must be less than VDD/VDDI specified in Section 6.4.