During power-down, VCC must be
supplied until after VBIAS, VRESET,
and VOFFSET are discharged to within the
specified limit of ground. See Table 9-1.
During power-down, it is a strict requirement
that the voltage difference between VBIAS and
VOFFSET must be within the specified
limit shown in Section 6.4.
During power-down, there is no requirement for the relative timing of VRESET with respect to VBIAS.
Power supply slew rates during power-down are
flexible, provided that the transient voltage levels follow
the requirements specified in Section 6.1, in Section 6.4, and in Figure 9-1.
During power-down, LVCMOS input pins must be less
than specified in Section 6.4.
B. To prevent excess
current, the supply voltage difference |VOFFSET – VBIAS| must be
less than the specified limit in the Section 6.4
C. To prevent excess
current, the supply difference |VBIAS – VRESET| must be less than
the specified limit in the Section 6.4.
D. VBIAS must power up
after VOFFSET has powered up, per the Delay1 specification in Table 9-1.
E. PG_OFFSET must turn
off after EN_OFFSET has turned off, per the Delay2 specification in
Table 9-1.
F. DLP®
controller software enables the DMD power supplies VBIAS, VRESET,
VOFFSET with VCC active after RESET_OEZ is at logic high.
G. DLP®
controller software initiates the global VBIAS command.
H. After the DMD micromirror park sequence is
complete, the DLP® controller
software initiates a hardware power-down that activates PWRDNZ and
disables VBIAS, VRESET, and VOFFSET.
I. Under power-loss
conditions where emergency DMD micromirror park procedures are being
enacted by the DLP®
controller hardware, EN_OFFSET may turn off after PG_OFFSET has
turned off. The OEZ signal goes high prior to PG_OFFSET turning off
to indicate the DMD micromirror has completed the emergency park
procedures.
Table 9-1 DMD
Power-Supply Requirements
PARAMETER
DESCRIPTION
MIN
NOM
MAX
UNIT
Delay1
Delay from
VOFFSET settled at recommended operating voltage to VBIAS power up