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ZHCSN33B November 2017 – February 2023 DLP550JE

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机械数据 (封装 | 引脚)

FYA|149
- MCLG018B

散热焊盘机械数据 (封装 | 引脚)

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zhcsn33b_oa

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted).#T4989946-2

		MIN	MAX	UNIT
SUPPLY VOLTAGES
V_CC	Supply voltage for LVCMOS core logic#T4989946-31	–0.5	4	V
V_CCI	Supply voltage for LVDS Interface#T4989946-31	–0.5	4	V
V_OFFSET	Micromirror Electrode and HVCMOS voltage#T4989946-31 #T4989946-33	–0.5	9	V
V_MBRST	Voltage applied to MBRST[0:15] Input Pins	–28	28	V
\|V_CC – V_CCI\|	Supply voltage change#DLPS101933		0.3	V
INPUT VOLTAGES
	Input voltage for all other input pins#T4989946-31	–0.5	V_CC + 0.3	V
\|V_ID\|	Input differential voltage (absolute value) #T4989946-32		700	mV
CLOCKS
ƒ_clock	Clock frequency for LVDS interface, DCLK_A		400	MHz
ƒ_clock	Clock frequency for LVDS interface, DCLK_B		400	MHz
ENVIRONMENTAL
T_ARRAY and T_WINDOW	Temperature, operating#DLPS1015831	0	90	°C
T_ARRAY and T_WINDOW	Temperature, non-operating #DLPS1015831	–40	90	°C
\|T_DELTA\|	Absolute Temperature delta between any point on the window edge and the ceramic test point TP1#DLPS1011043		30	°C
T_DP	Dew Point Temperature, operating and non-operating (non-condensing)		81	°C

(1) All voltages are referenced to common ground V_SS. Voltages V_CC, V_CCI, and V_OFFSET are required for proper DMD operation. V_SS must also be connected.

(2) V_OFFSET supply transients must fall within specified voltages.

(3) Exceeding the recommended allowable absolute voltage difference between V_CC and V_CCI may result in excess current draw.

(4) This maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.

(5) The highest temperature of the active array (as calculated by the GUID-BBB8F296-C115-47E9-9B94-CDBFBB476EDC.html#GUID-BBB8F296-C115-47E9-9B94-CDBFBB476EDC) or of any point along the Window Edge as defined in GUID-BBB8F296-C115-47E9-9B94-CDBFBB476EDC.html#DLPS101965477. The locations of thermal test points TP2, TP3, TP4, and TP5 in GUID-BBB8F296-C115-47E9-9B94-CDBFBB476EDC.html#DLPS101965477 are intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, that point should be used.

(6) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in GUID-BBB8F296-C115-47E9-9B94-CDBFBB476EDC.html#DLPS101965477. The window test points TP2, TP3, TP4, and TP5 shown in GUID-BBB8F296-C115-47E9-9B94-CDBFBB476EDC.html#DLPS101965477 are intended to result in the worst-case delta. If a particular application causes another point on the window edge to result in a larger delta temperature, that point should be used.

(7) Stresses beyond those listed under #GUID-6267F3F2-F83A-40EA-9D2B-C2D526C613BF may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under GUID-4099E5F6-AAA6-418E-9C70-AB9F6B9ED0B7.html#GUID-4099E5F6-AAA6-418E-9C70-AB9F6B9ED0B7. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.