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ZHCSD21 October 2014 DLP6500FLQ

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FLQ|203

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted) ⁽¹⁾

SUPPLY VOLTAGES		MIN	MAX	UNIT
VCC	Supply voltage for LVCMOS core logic ⁽²⁾	–0.5	4	V
VCCI	Supply voltage for LVDS receivers ⁽²⁾	–0.5	4	V
VOFFSET	Supply voltage for HVCMOS and micromirror electrode⁽²⁾⁽³⁾	–0.5	9	V
VBIAS	Supply voltage for micromirror electrode ⁽²⁾	–0.5	17	V
VRESET	Supply voltage for micromirror electrode⁽²⁾	–11	0.5	V
\| VCC – VCCI \|	Supply voltage delta (absolute value) ⁽⁴⁾		0.3	V
\| VBIAS – VOFFSET \|	Supply voltage delta (absolute value)⁽⁵⁾		8.75	V
INPUT VOLTAGES
	Input voltage for all other LVCMOS input pins ⁽²⁾	–0.5	VCC + 0.3	V
	Input voltage for all other LVDS input pins⁽²⁾	–0.5	VCCI + 0.3	V
\|V_ID\|	Input differential voltage (absolute value)⁽²⁾⁽⁶⁾		700	mV
I_ID	Input differential current ⁽⁷⁾		7	mA
CLOCKS
ƒ_clock	Clock frequency for LVDS interface, DCLK_A		460	MHz
	Clock frequency for LVDS interface, DCLK_B		460	MHz
	Clock frequency for LVDS interface, DCLK_C		460	MHz
	Clock frequency for LVDS interface, DCLK_D		460	MHz
ENVIRONMENTAL
T_CASE	Case temperature: operational⁽⁸⁾⁽⁹⁾	0	70	°C
T_CASE	Case temperature: non–operational ⁽⁹⁾	–40	80	°C
	Differential temperature⁽⁸⁾		10	°C
	Operating relative humidity ( non-condensing )	0	95%

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device is not implied at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure above Recommended Operating Conditions for extended periods may affect device reliability.

(2) All voltages are referenced to common ground VSS. Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected.

(3) VOFFSET supply transients must fall within specified voltages.

(4) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit.

(5) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit. Refer to Power Supply Recommendations for additional information.

(6) This maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.

(7) LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.

(8) Exposure of the DMD simultaneously to any combination of the maximum operating conditions for case temperature, differential temperature, or illumination power density will reduce device lifetime. Refer to Handling Ratings.

(9) DMD Temperature is the worst-case of any thermal test point in Figure 15, or the active array as calculated by the Micromirror Array Temperature Calculation.

6.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage temperature range (non-operating)⁽¹⁾⁽²⁾⁽³⁾		–40	80	°C
T_stg	Storage humidity, non – condensing⁽¹⁾⁽²⁾⁽³⁾		0%	95%	RH
V_(ESD)	Electrostatic discharge	All pins, human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽⁴⁾		2000	V

(1) Simultaneous exposure to high storage temperature and high storage humidity may affect device reliability.

(2) As a best practice, TI recommends storing the DMD in a temperature and humidity controlled environment.

(3) Optimal, long-term performance of the DMD can be affected by ambient storage temperature and ambient storage humidity.

(4) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
SUPPLY VOLTAGES⁽¹⁾⁽²⁾
VCC	Supply voltage for LVCMOS core logic	3.0	3.3	3.6	V
VCCI	Supply voltage for LVDS receivers	3.0	3.3	3.6	V
VOFFSET	Supply voltage for HVCMOS and micromirror electrodes⁽³⁾	8.25	8.5	8.75	V
VBIAS	Supply voltage for micromirror electrodes	15.5	16	16.5	V
VRESET	Mirror electrode voltage	–9.5	–10	–10.5	V
\| VCCI–VCC \|	Supply voltage delta (absolute value) ⁽⁴⁾			0.3	V
\| VBIAS–VOFFSET \|	Supply voltage delta (absolute value) ⁽⁵⁾			8.75	V
LVCMOS PINS
V_IH	High level Input voltage⁽⁶⁾	1.7	2.5	VCC + 0.3	V
V_IL	Low level Input voltage⁽⁶⁾	–0.3		0.7	V
I_OH	High level output current at VOH = 2.4 V			–20	mA
I_OL	Low level output current at VOL = 0.4 V			15	mA
T_PWRDNZ	PWRDNZ pulse width⁽⁷⁾	10			ns
SCP INTERFACE⁽⁵⁾
ƒ_clock	SCP clock frequency⁽⁸⁾			500	kHz
t_{SCP_SKEW}	Time between valid SCPDI and rising edge of SCPCLK⁽⁹⁾	–800		800	ns
t_{SCP_DELAY}	Time between valid SCPDO and rising edge of SCPCLK⁽⁹⁾			700	ns
t_{SCP_BYTE_INTERVAL_}	Time between consecutive bytes	1			µs
t_{SCP_NEG_ENZ}	Time between falling edge of SCPENZ and the first rising edge of SCPCLK	30			ns
t_{SCP_PW_ENZ}	SCPENZ inactive pulse width (high level)	1			µs
t_{SCP_OUT_EN}	Time required for SCP output buffer to recover after SCPENZ (from tri-state)			1.5	ns
ƒ_clock	SCP circuit clock oscillator frequency⁽¹⁰⁾	9.6		11.1	MHz
LVDS INTERFACE
ƒ_clock	Clock frequency DCLK			400	MHz
\| V_ID \|	Input differential voltage (absolute value)⁽¹¹⁾	100	400	600	mV
V_CM	Common mode⁽¹¹⁾		1200		mV
V_LVDS	LVDS voltage⁽¹¹⁾	0		2000	mV
t_{LVDS_RSTZ}	Time required for LVDS receivers to recover from PWRDNZ			10	ns
Z_IN	Internal differential termination resistance	95		105	Ω
Z_LINE	Line differential impedance (PWB/trace)	90	100	110	Ω
ENVIRONMENTAL⁽¹²⁾	For Illumination Source between 420 and 700 nm
T_DMD	DMD temperature – operational⁽¹³⁾⁽¹⁴⁾	10		40 to 70⁽¹⁴⁾	°C
T_WINDOW	Window temperature – operational			70	°C
T_GRADIENT	Device temperature gradient – operational⁽¹⁵⁾			10	°C
ILL_VIS	Illumination, wavelengths between 420 and 700 nm			Thermally Limited⁽¹⁶⁾	mW /cm2
ENVIRONMENTAL⁽¹²⁾	For Illumination Source between 400 and 420 nm
T_DMD	DMD temperature – operational⁽¹³⁾⁽¹⁴⁾	20		30⁽¹⁴⁾	°C
T_GRADIENT	Device temperature gradient – operational ⁽¹⁵⁾			10	°C
ILL_VIS	Illumination, wavelengths between 400 and 420 nm			2.5	W/cm2
ENVIRONMENTAL⁽¹²⁾	For Illumination Source <420 and >700 nm
T_DMD	DMD temperature – operational⁽¹³⁾⁽¹⁴⁾	10		40 to 70⁽¹⁴⁾	°C
T_WINDOW	Window temperature – operational			70	°C
T_GRADIENT	Device temperature gradient – operational⁽¹⁵⁾			10	°C
ILL_UV	Illumination, wavelength < 400 nm			0.68	mW /cm2
ILL_IR	Illumination, wavelength > 700 nm			10	mW /cm2

(1) Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected.

(2) All voltages are referenced to common ground VSS.

(3) VOFFSET supply transients must fall within specified max voltages.

(4) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit.

(5) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit. Refer to Power Supply Recommendations for additional information.

(6) Tester Conditions for VIH and VIL:
Frequency = 60MHz. Maximum Rise Time = 2.5ns @ (20% to 80%)
Frequency = 60MHz. Maximum Fall Time = 2.5ns @ (80% to 20%)

(7) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tri-states the SCPDO output pin.

(8) The SCP clock is a gated clock. Duty cycle shall be 50% ± 10%. SCP parameter is related to the frequency of DCLK.

(9) Refer to Figure 3.

(10) SCP internal oscillator is specified to operate all SCP registers. For all SCP operations, DCLK is required.

(11) Refer to Figure 4 , Figure 5 , and Figure 6.

(12) Optimal, long-term performance and optical effciency of the Digital Micromirror Device (DMD) can be affected by various application parameters, including illumination spectrum, illumination power density, micromirror landed duty-cycle, ambient temperature (storage and operating), DMD temperature, ambient humidity (storage and operating), and power on or off duty cycle. TI recommends that application-specific effects be considered as early as possible in the design cycle.

(13) DMD Temperature is the worst-case of any thermal test point in Figure 15, or the active array as calculated by the Micromirror Array Temperature Calculation.

(14) Per Figure 1, the maximum operational case temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. Refer to Micromirror Landed-on/Landed-Off Duty Cycle for a definition of micromirror landed duty cycle.

(15) As measured between any two points on the exterior of the package, or as predicted between any two points inside the micromirror array cavity. Refer to Thermal Information and Micromirror Array Temperature Calculation.

(16) Refer to Thermal Information and Micromirror Array Temperature Calculation.

Figure 1. Max Recommended DMD Temperature – Derating Curve

6.4 Thermal Information

THERMAL METRIC⁽¹⁾	MIN	DLP6500FLQ FLQ (203)	MAX	UNIT
Active Area to Case Ceramic Thermal resistance ⁽¹⁾			0.7	°C/W

(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package where it can be removed by an appropriate heat sink. The heat sink and cooling system must be capable of maintaining the package within the temperature range specified in the Recommended Operating Conditions.
The total heat load on the DMD is largely driven by the incident light absorbed by the active area; although other contributions include light energy absorbed by the window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER	DESCRIPTION	TEST CONDITIONS⁽¹⁾	MIN	MAX	UNIT
V_OH	High-level output voltage	VCC = 3 V, I_OH = –20 mA	2.4		V
V_OL	Low level output voltage	VCC = 3.6 V, I_OL = 15 mA		0.4	V
I_IH	High–level input current⁽²⁾⁽³⁾	VCC = 3.6 V , VI = VCC		250	µA
IIL	Low level input current	VCC = 3.6 V, V_I = 0	–250		µA
I_OZ	High–impedance output current	VCC = 3.6 V		10	µA
CURRENT
I_CC	Supply current⁽⁴⁾	VCC = 3.6 V		1076	mA
I_CCI	Supply current⁽⁴⁾	VCCI = 3.6 V		518	mA
I_OFFSET	Supply current⁽⁵⁾	V_OFFSET = 8.75 V		4	mA
I_BIAS	Supply current⁽⁵⁾	V_BIAS = 16.5 V		14	mA
I_RESET	Supply current	V_RESET = –10.5 V		11	mA
I_TOTAL	Supply current	Total Sum		1623	mA
POWER
P_CC	Supply power dissipation	VCC = 3.6 V		3874	mW
P_CCI		VCCI = 3.6 V		1865
P_OFFSET		V_OFFSET = 8.75 V		35
P_BIAS		V_BIAS = 16.5 V		231
P_RESET		V_RESET = –10.5 V		116
P_TOTAL	Supply power dissipation⁽⁶⁾	Total Sum		6300
CAPACITANCE
C_I	Input capacitance	ƒ = 1 MHz		10	pF
C_O	Output capacitance	ƒ = 1 MHz		10	pF
C_M	Reset group capacitance MBRST(14:0)	ƒ = 1 MHz; 1920 × 72 micromirrors	330	390	pF

(1) All voltages are referenced to common ground VSS. Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected.

(2) Applies to LVCMOS input pins only. Does not apply to LVDS pins and MBRST pins.

(3) LVCMOS input pins utilize an internal 18000 Ω passive resistor for pull-up and pull-down configurations. Refer to Pin Configuration and Functions to determine pull-up or pull-down configuration used.

(4) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit.

(5) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.

(6) Total power on the active micromirror array is the sum of the electrical power dissipation and the absorbed power from the illumination source. See the Micromirror Array Temperature Calculation.

6.6 Timing Requirements

Over Recommended Operating Conditions unless otherwise noted.

		DESCRIPTION⁽¹⁾		MIN	TYP	MAX	UNIT
SCP INTERFACE⁽²⁾
t_r	Rise time	20% to 80%				200	ns
t_ƒ	Fall time	80% to 20%				200	ns
LVDS INTERFACE⁽²⁾
t_r	Rise time	20% to 80%		100		400	ps
t_ƒ	Fall time	80% to 20%		100		400	ps
LVDS CLOCKS⁽³⁾
t_c	Cycle time	DCLK_A, 50% to 50%		2.5			ns
t_c	Cycle time	DCLK_B, 50% to 50%		2.5			ns
t_w	Pulse duration	DCLK_A, 50% to 50%		1.19	1.25		ns
t_w	Pulse duration	DCLK_B, 50% to 50%		1.19	1.25		ns
LVDS INTERFACE⁽³⁾
t_su	Setup time	D_A(15:0) before rising or falling edge of DCLK_A		0.2			ns
t_su	Setup time	D_B(15:0) before rising or falling edge of DCLK_B		0.2			ns
t_su	Setup time	SCTRL_A before rising or falling edge of DCLK_A		0.2			ns
t_su	Setup time	SCTRL_B before rising or falling edge of DCLK_B		0.2			ns
t_h	Hold time	D_A(15:0) after rising or falling edge of DCLK_A		0.5			ns
t_h	Hold time	D_B(15:0) after rising or falling edge of DCLK_B		0.5			ns
t_h	Hold time	SCTRL_A after rising or falling edge of DCLK_A		0.5			ns
t_h	Hold time	SCTRL_B after rising or falling edge of DCLK_B		0.5			ns
LVDS INTERFACE⁽⁴⁾
t_skew	Skew time	Channel B relative to Channel A	Channel A includes the following LVDS pairs: DCLK_AP and DCLK_AN SCTRL_AP and SCTRL_AN D_AP(15:0) and D_AN(15:0)	–1.25		1.25	ns
t_skew	Skew time	Channel B relative to Channel A	Channel B includes the following LVDS pairs: DCLK_BP and DCLK_BN SCTRL_BP and SCTRL_BN D_BP(15:0) and D_BN(15:0)	–1.25		1.25	ns

(1) Refer to Pin Configuration and Functions for pin details.

(2) Refer to Figure 7

(3) Refer to Figure 8

(4) Refer to Figure 9

Timing Diagrams

The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. Figure 2 shows an equivalent test load circuit for the output under test. The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving.

Timing reference loads are not intended as a precise representation of any particular system environment or depiction of the actual load presented by a production test. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Refer to the Application and Implementation section.

Figure 2. Test Load Circuit

Not to scale.

Refer to SCP Interface section of the Recommended Operating Conditions table.

Figure 3. SCP Timing Parameters

Refer to the LVDS Interface section of the Recommended Operating Conditions table.

Refer to Pin Configuration and Functions for a list of LVDS pins.

Figure 4. LVDS Voltage Definitions (References)

Not to scale.

Refer to the LVDS Interface section of the Recommended Operating Conditions table.

Figure 5. LVDS Voltage Parameters

Refer to LVDS Interface section of the Recommended Operating Conditions table

Refer to Pin Configuration and Functions for list of LVDS pins.

Figure 6. LVDS Equivalent Input Circuit

Not to scale.

Refer to the Timing Requirements table.

Refer to Pin Configuration and Functions for list of LVDS pins and SCP pins.

Figure 7. Rise Time and Fall Time

Not to scale.

Refer to LVDS INTERFACE section in the Timing Requirements table.

Figure 8. Timing Requirement Parameter Definitions

Not to scale.

Refer to LVDS INTERFACE in the Timing Requirements table.

Figure 9. LVDS Interface Channel Skew Definition

6.7 Typical Characteristics

The DLP6500 DMD is controlled by the DLPC900 controller. The controller has two modes of operation. The first is Video mode where the video source is displayed on the DMD. The second is Pattern mode, where the patterns are pre-stored in flash memory and then streamed to the DMD. The allowed DMD pattern rate depends on which mode and bit-depth is selected.

Table 1. Bit Depth versus Pattern Rate

BIT DEPTH	VIDEO MODE RATE (Hz)	PATTERN MODE RATE (Hz)
1	2880	9523
2	1440	3289
3	960	2638
4	720	1364
5	480	823
6	480	672
7	360	500
8	247	247

6.8 System Mounting Interface Loads

PARAMETER			MAX	UNIT
Maximum system mounting interface load to be applied to the:	Thermal Interface area	(See Figure 10)	25	lbs
			95	lbs
	Electrical Interface area
	Datum “A” Interface area⁽¹⁾
	Datum “A” Interface area⁽¹⁾		90	lbs

(1) Combined loads of the thermal and electrical interface areas in excess of Datum “A” load shall be evenly distributed outside the Datum “A” area (95 + 25 – Datum “A).

Figure 10. System Mounting Interface Loads

6.9 Micromirror Array Physical Characteristics

				VALUE	UNIT
M	Number of active columns		See Figure 11	1920	micromirrors
N	Number of active rows			1080	micromirrors
P	Micromirror (pixel) pitch			7.56	µm
	Micromirror active array width	M × P		14.5152	mm
	Micromirror active array height	N × P		8.1648	mm
	Micromirror active border	Pond of micromirror (POM)⁽¹⁾		14	micromirrors /side

(1) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM. These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical bias to tilt toward OFF.

Refer to section Micromirror Array Physical Characteristics table for M, N, and P specifications.

Figure 11. Micromirror Array Physical Characteristics

6.10 Micromirror Array Optical Characteristics

See Optical Interface and System Image Quality for important information.

PARAMETER		CONDITIONS	MIN	NOM	MAX	UNIT
α	Micromirror tilt angle	DMD landed state ⁽¹⁾		12		°
β	Micromirror tilt angle tolerance⁽¹⁾⁽²⁾⁽³⁾⁽⁴⁾⁽⁵⁾		–1		1	°
	Micromirror tilt direction⁽⁵⁾⁽⁶⁾⁽⁷⁾	Figure 12	44	45	46	°
	Number of out-of-specification micromirrors ⁽⁷⁾	Adjacent micromirrors			0	micromirrors
	Number of out-of-specification micromirrors ⁽⁷⁾	Non-adjacent micromirrors			10	micromirrors
	Micromirror crossover time ⁽⁸⁾⁽⁹⁾	Typical performance		2.5		μs
	Micromirror switching time ⁽⁹⁾	Typical performance		5		μs
	DMD efficiency within the wavelength range 400 nm to 420 nm⁽¹⁰⁾			68%
	DMD photopic efficiency within the wavelength range 420 nm to 700 nm⁽¹⁰⁾			66%

(1) Measured relative to the plane formed by the overall micromirror array.

(2) Additional variation exists between the micromirror array and the package datums.

(3) Represents the landed tilt angle variation relative to the nominal landed tilt angle.

(4) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different devices.

(5) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result in colorimetry variations, system efficiency variations or system contrast variations.

(6) When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON State direction. A binary value of 0 results in a micromirror landing in the OFF State direction.

(7) An out-of-specification micromirror is defined as a micromirror that is unable to transition between the two landed states within the specified Micromirror Switching Time

(8) Micromirror crossover time is primarily a function of the natural response time of the micromirrors.

(9) Performance as measured at the start of life.

(10) Efficiency numbers assume 24-degree illumination angle, F/2.4 illumination and collection cones, uniform source spectrum, and uniform pupil illumination. Efficiency numbers assume 100% electronic mirror duty cycle and do not include optical overfill loss. Note that this number is specified under conditions described above and deviations from the specified conditions could result in decreased efficiency.

Refer to section Micromirror Array Physical Characteristics table for M, N, and P specifications.

Figure 12. Micromirror Landed Orientation and Tilt

6.11 Window Characteristics

PARAMETER⁽¹⁾	CONDITIONS	MIN	TYP
Window material designation	Corning 7056
Window refractive index	at wavelength 589 nm		1.487
Window aperture⁽²⁾	See⁽²⁾
Illumination overfill⁽³⁾	See⁽³⁾
Window transmittance, single–pass through both surfaces and glass ⁽⁴⁾	At wavelength 405 nm. Applies to 0° and 24° AOI only.	95%
	Minimum within the wavelength range 420 nm to 680 nm. Applies to all angles 0° to 30° AOI.	97%
	Average over the wavelength range 420 nm to 680 nm. Applies to all angles 30° to 45° AOI.	97%

(1) See Window Characteristics and Optics for more information.

(2) For details regarding the size and location of the window aperture, see the package mechanical characteristics listed in the Mechanical ICD in section Mechanical, Packaging, and Orderable Information.

(3) Refer to Illumination Overfill.

(4) See the TI application report DLPA031, Wavelength Transmittance Considerations for DLP™ DMD Window.

6.12 Chipset Component Usage Specification

The DLP6500FLQ is a component of one or more DLP® chipsets. Reliable function and operation of the DLP6500FLQ requires that it be used in conjunction with the other components of the applicable DLP chipset, including those components that contain or implement TI DMD control technology. TI DMD control technology is the TI technology and devices for operating or controlling a DLP DMD.