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ZHCSRS7A August 2017 – February 2023 DLP650NE

PRODUCTION DATA

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机械数据 (封装 | 引脚)

FYE|350

散热焊盘机械数据 (封装 | 引脚)

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6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by this table. No level of performance is implied when operating the device above or below these limits.

		MIN	NOM	MAX	UNIT
SUPPLY VOLTAGES⁽¹⁾⁽²⁾
VCC	Supply voltage for LVCMOS core logic	3.15	3.3	3.45	V
VCCI	Supply voltage for LVDS receivers	3.15	3.3	3.45	V
VOFFSET	Supply voltage for HVCMOS and micromirror electrodes⁽²⁾	8.25	8.5	8.75	V
VBIAS	Supply voltage for micromirror electrodes	15.5	16	16.5	V
VRESET	Supply voltage for micromirror electrodes	–9.5	–10	–10.5	V
\|VCCI–VCC\|	Supply voltage change (absolute value)⁽³⁾		0	0.3	V
\|VBIAS–VOFFSET\|	Supply voltage change (absolute value)⁽⁴⁾			8.75	V
LVCMOS PINS
V_IH	High level Input voltage⁽⁵⁾	1.7	2.5	VCC + 0.15	V
V_IL	Low level Input voltage⁽⁵⁾	– 0.3		0.7	V
I_OH	High level output current at V_OH = 2.4 V			–20	mA
I_OL	Low level output current at V_OL = 0.4 V			15	mA
t_PWRDNZ	PWRDNZ pulse width⁽⁶⁾	10			ns
SCP INTERFACE
ƒ_SCPCLK	SCP clock frequency⁽⁷⁾			500	kHz
t_{SCP_DS}	SCPDI clock setup time (before SCPCLK falling-edge)⁽⁸⁾	800			ns
t_{SCP_DH}	SCPDI hold time (after SCPCLK falling-edge)⁽⁸⁾	900			ns
t_{SCP_BYTE_INTERVAL}	Time between consecutive bytes	1			µs
t_{SCP_NEG_ENZ}	Time between falling edge of SCPENZ and the first rising edge of SCPCLK	30			ns
t_{SCP_PW_ENZ}	SCPENZ inactive pulse width (high level)	1			µs
t_{SCP_OUT_EN}	Time required for SCP output buffer to recover after SCPENZ (from tristate)			1.5	ns
ƒ_clock	SCP circuit clock oscillator frequency⁽⁹⁾	9.6		11.1	MHz
LVDS INTERFACE
ƒ_clock	Clock frequency for LVDS interface, DCLK (all channels)			400	MHz
\|V_ID\|	Input differential voltage (absolute value)⁽¹⁰⁾	100	400	600	mV
V_CM	Common mode⁽¹⁰⁾		1200		mV
V_LVDS	LVDS voltage⁽¹⁰⁾	0		2000	mV
t_{LVDS_RSTZ}	Time required for LVDS receivers to recover from PWRDNZ			10	ns
Z_IN	Internal differential termination resistance	95		105	Ω
Z_LINE	Line differential impedance (PWB/trace)	90	100	110	Ω
ENVIRONMENTAL
T_ARRAY	Array temperature, long-term operational⁽¹¹⁾⁽¹²⁾⁽¹³⁾	10		40 to 70⁽¹⁴⁾	°C
T_ARRAY	Array temperature, short-term operational⁽¹²⁾⁽¹⁵⁾	0		10	°C
T_WINDOW	Window temperature – operational⁽¹⁶⁾			85	°C
T_{\|DELTA \|}	Absolute temperature delta between any point on the window edge and the ceramic test point TP1.⁽¹⁷⁾⁽¹⁸⁾			26	°C
T_DP-AVG	Average dew point temperature (non-condensing)⁽¹⁹⁾			28	°C
T_DP-ELR	Elevated dew point temperature range (non-condensing)⁽²⁰⁾	28		36	°C
CT_ELR	Cumulative time in elevated dew point temperature range			24	Months
L	Operating system luminance⁽¹⁸⁾			4200	lm
ILL_UV	Illumination, wavelength < 395 nm⁽¹¹⁾		0.68	2.0	mW/cm²
ILL_VIS	Illumination, wavelength between 395 nm and 800 nm	Thermally Limited
ILL_IR	Illumination, wavelength > 800 nm			10	mW/cm²

(1) Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected.

(2) VOFFSET supply transients must fall within specified max voltages.

(3) To prevent excess current, the supply voltage change |VCCI – VCC| must be less than specified limit.

(4) To prevent excess current, the supply voltage change |VBIAS – VOFFSET| must be less than specified limit. Refer to Section 8 for additional information.

(5) Tester conditions for V_IH and V_IL:
Frequency = 60 MHz. Maximum Rise Time = 2.5 ns at (20% to 80%)
Frequency = 60 MHz. Maximum Fall Time = 2.5 ns at (80% to 20%)

(6) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tri-states the SCPDO output pin.

(7) The SCP clock is a gated clock. Duty cycle shall be 50% ± 10%. SCP parameter is related to the frequency of DCLK.

(8) Refer to Figure 6-2.

(9) SCP internal oscillator is specified to operate all SCP registers. For all SCP operations, DCLK is required.

(10) Refer to Figure 6-3, Figure 6-4, and Figure 6-5.

(11) Simultaneous exposure of the DMD to the maximum Section 6.4 for temperature and UV illumination reduces device lifetime.

(12) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1) shown in Figure 7-1 and the package thermal resistance using the calculation in Section 7.6.

(13) Long-term is defined as the average over the usable life.

(14) Per Figure 6-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. See Section 7.7.

(15) Array temperatures beyond those specified as long-term are recommended for short-term conditions only (power-up). Short-term is defined as cumulative time over the usable life of the device and is less than 500 hours.

(16) The locations of thermal test points TP2, TP3, TP4 and TP5 in Figure 7-1 are intended to measure the highest window edge temperature. For most applications, the locations shown are representative of the highest window edge temperature. If a particular application causes additional points on the window edge to be at a higher temperature, test points should be added to those locations.

(17) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in Figure 7-1. The window test points TP2, TP3, TP4, and TP5 shown in Figure 7-1 are intended to result in the worst-case delta temperature. If a particular application causes another point on the window edge to result in a larger delta in temperature, that point should be used.

(18) DMD is qualified at the combination of the maximum temperature and maximum lumens specified. Operation of the DMD outside of these limits has not been tested.

(19) The average over time (including storage and operating) that the device is not in the 'elevated dew point temperature range'.

(20) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative time of CT_ELR.

Figure 6-1 Recommended Maximum DMD Temperature—Derating Curve