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DLPS036B September 2014 – October 2016 DLP9000

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FLS|355
- MCLG031B

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

			MIN	MAX	UNIT
SUPPLY VOLTAGES
VCC	Supply voltage for LVCMOS core logic ⁽²⁾		–0.5	4	V
VCCI	Supply voltage for LVDS receivers ⁽²⁾		–0.5	4	V
VOFFSET	Supply voltage for HVCMOS and micromirror electrode ⁽²⁾ ⁽³⁾		–0.5	9	V
VBIAS	Supply voltage for micromirror electrode ⁽²⁾		–0.5	17	V
VRESET	Supply voltage for micromirror electrode ⁽²⁾		–11	0.5	V
\| VCC – VCCI \|	Supply voltage delta (absolute value) ⁽⁴⁾			0.3	V
\| VBIAS – VOFFSET \|	Supply voltage delta (absolute value) ⁽⁵⁾			8.75	V
INPUT VOLTAGES
	Input voltage for all other LVCMOS input pins ⁽²⁾		–0.5	VCC + 0.3	V
	Input voltage for all other LVDS input pins ⁽²⁾ ⁽⁶⁾		–0.5	VCCI + 0.3	V
\| V_ID \|	Input differential voltage (absolute value) ⁽⁷⁾			700	mV
I_ID	Input differential current ⁽⁷⁾			7	mA
CLOCKS
ƒ_clock	DLP9000	Clock frequency for LVDS interface, DCLK_A		440	MHz
		Clock frequency for LVDS interface, DCLK_B		440
		Clock frequency for LVDS interface, DCLK_C		440
		Clock frequency for LVDS interface, DCLK_D		440
	DLP9000X	Clock frequency for LVDS interface, DCLK_A		500
		Clock frequency for LVDS interface, DCLK_B		500
		Clock frequency for LVDS interface, DCLK_C		500
		Clock frequency for LVDS interface, DCLK_D		500
ENVIRONMENTAL
T_ARRAY	Array temperature: operational ⁽⁸⁾ ⁽⁹⁾		0	90	ºC
T_ARRAY	Array temperature: non–operational ⁽⁹⁾		-40	90	ºC
T_WINDOW	Window temperature: operational		0	70	ºC
T_WINDOW	Window temperature: non–operational		-40	90	ºC
\|T_DELTA\|	Absolute termperature delta between the window test points and the ceramic test point TP1⁽¹⁰⁾			10	ºC
RH	Relative Humidity, operating and non–operating			95%

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device is not implied at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure above Recommended Operating Conditions for extended periods may affect device reliability.

(2) All voltages are referenced to common ground VSS. Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected.

(3) VOFFSET supply transients must fall within specified voltages.

(4) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit.

(5) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit. Refer to Power Supply Requirements for additional information.

(6) This maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.

(7) LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.

(8) Exposure of the DMD simultaneously to any combination of the maximum operating conditions for case temperature, differential temperature, or illumination power density may affect device reliability.

(9) The highest temperature of the active array as calculated by the Micromirror Array Temperature Calculation using ceramic test point 1 (TP1) in Figure 15.

(10) Temperature delta is the highest difference between the ceramic test point TP1 and window test points TP2 and TP3 in Figure 15.

7.2 Storage Conditions

applicable before the DMD is installed in the final product

			MIN	MAX	UNIT
T_DMD		DMD storage temperature	-40	80	°C
RH		Relative Humidity, (non-condensing)		95%

7.3 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins ⁽¹⁾	±2000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	NOM	MAX	UNIT
SUPPLY VOLTAGES ⁽¹⁾ ⁽²⁾
VCC	DLP9000	Supply voltage for LVCMOS core logic	3.0	3.3	3.6	V
VCC	DLP9000X	Supply voltage for LVCMOS core logic	3.3	3.45	3.6	V
VCCI	DLP9000	Supply voltage for LVDS receivers	3.0	3.3	3.6	V
VCCI	DLP9000X	Supply voltage for LVDS receivers	3.3	3.45	3.6	V
VOFFSET	Supply voltage for HVCMOS and micromirror electrodes ⁽³⁾		8.25	8.5	8.75	V
VBIAS	Supply voltage for micromirror electrodes		15.5	16	16.5	V
VRESET	Supply voltage for micromirror electrodes		–9.5	–10	–10.5	V
\|VCCI–VCC\|	Supply voltage delta (absolute value) ⁽⁴⁾				0.3	V
\|VBIAS–VOFFSET\|	Supply voltage delta (absolute value) ⁽⁵⁾				8.75	V
LVCMOS PINS
V_IH	High level Input voltage ⁽⁶⁾		1.7	2.5	VCC + 0.3	V
V_IL	Low level Input voltage ⁽⁶⁾		– 0.3		0.7	V
I_OH	High level output current at V_OH = 2.4 V				–20	mA
I_OL	Low level output current at V_OL = 0.4 V				15	mA
T_PWRDNZ	PWRDNZ pulse width ⁽⁷⁾		10			ns
SCP INTERFACE
ƒ_clock	SCP clock frequency ⁽⁸⁾				500	kHz
t_{SCP_SKEW}	Time between valid SCPDI and rising edge of SCPCLK ⁽¹⁷⁾		–800		800	ns
t_{SCP_DELAY}	Time between valid SCPDO and rising edge of SCPCLK ⁽¹⁷⁾				700	ns
t_{SCP_BYTE_INTERVAL}	Time between consecutive bytes		1			µs
t_{SCP_NEG_ENZ}	Time between falling edge of SCPENZ and the first rising edge of SCPCLK		30			ns
t_{SCP_PW_ENZ}	SCPENZ inactive pulse width (high level)		1			µs
t_{SCP_OUT_EN}	Time required for SCP output buffer to recover after SCPENZ (from tri-state)				1.5	ns
ƒ_clock	SCP circuit clock oscillator frequency ⁽⁹⁾		9.6		11.1	MHz
LVDS INTERFACE
ƒ_clock	DLP9000	Clock frequency DCLK			400	MHz
ƒ_clock	DLP9000X	Clock frequency DCLK ⁽¹⁰⁾	400		480	MHz
\|V_ID\|	Input differential voltage (absolute value) ⁽¹⁸⁾		100	400	600	mV
V_CM	Common mode ⁽¹⁸⁾			1200		mV
V_LVDS	LVDS voltage ⁽¹⁸⁾		0		2000	mV
t_{LVDS_RSTZ}	Time required for LVDS receivers to recover from PWRDNZ				10	ns
Z_IN	Internal differential termination resistance		95		105	Ω
Z_LINE	Line differential impedance (PWB/trace)		90	100	110	Ω
ENVIRONMENTAL ⁽¹¹⁾ For Illumination Source Between 420 nm and 700 nm
T_ARRAY	DLP9000	Array temperature, Long–term operational ⁽¹³⁾ ⁽¹²⁾⁽¹⁹⁾	10		40 to 65 ⁽¹⁴⁾	°C
	DLP9000	Array temperature, Short–term operational ⁽¹³⁾ ⁽¹²⁾⁽²⁰⁾	0		10
	DLP9000X	Array temperature, Long–term operational ⁽¹³⁾ ⁽¹²⁾⁽¹⁹⁾	10		40 ⁽²¹⁾
	DLP9000X	Array temperature, Short–term operational ⁽¹³⁾ ⁽¹²⁾⁽²⁰⁾	0		10
T_WINDOW	DLP9000	Window Temperature test points TP2 and TP3, Long-term operational⁽¹⁹⁾	10		70	°C
T_WINDOW	DLP9000X	Window Temperature test points TP2 and TP3, Long-term operational⁽¹⁹⁾	10		40	°C
\|T_DELTA\|	Absolute Temperature delta between the window test points (TP2, TP3) and the ceramic test point TP1⁽¹⁵⁾				10	°C
ILL_VIS	Illumination				Thermally Limited ⁽¹⁶⁾	mW/cm²
RH	Relative Humidity (non-condensing)				95%
ENVIRONMENTAL ⁽¹¹⁾ For Illumination Source Between 400 nm and 420 nm
T_ARRAY	Array temperature, Long–term operational ⁽¹³⁾ ⁽¹²⁾⁽¹⁹⁾		20		30	°C
T_ARRAY	Array temperature, Short–term operational ⁽¹³⁾ ⁽¹²⁾⁽²⁰⁾		0		20	°C
T_WINDOW	Window Temperature test points TP2 and TP3, Long-term operational⁽¹⁹⁾				30	°C
\|T_DELTA\|	Absolute Temperature delta between the window test points (TP2, TP3) and the ceramic test point TP1⁽¹⁵⁾				10	°C
ILL_VIS	Illumination				10	W/cm²
RH	Relative Humidity (non-condensing)				95%
ENVIRONMENTAL ⁽¹¹⁾ For Illumination Source <400 nm and >700 nm
T_ARRAY	DLP9000	Array temperature, Long–term operational ⁽¹³⁾ ⁽¹²⁾⁽¹⁹⁾	10		40 to 65 ⁽¹⁴⁾	°C
	DLP9000	Array temperature, Short–term operational ⁽¹³⁾ ⁽¹²⁾⁽²⁰⁾	0		10
	DLP9000X	Array temperature, Long–term operational ⁽¹³⁾ ⁽¹²⁾⁽¹⁹⁾	10		40 ⁽²¹⁾
	DLP9000X	Array temperature, Short–term operational ⁽¹³⁾ ⁽¹²⁾⁽²⁰⁾	0		10
T_WINDOW	DLP9000	Window Temperature test points TP2 and TP3, Long-term operational⁽¹⁹⁾	10		70	°C
T_WINDOW	DLP9000X	Window Temperature test points TP2 and TP3, Long-term operational⁽¹⁹⁾	10		40	°C
\|T_DELTA\|	Absolute Temperature delta between the window test points (TP2, TP3) and the ceramic test point TP1⁽¹⁵⁾				10	°C
ILL_UV	Illumination, wavelength < 400 nm				0.68	mW/cm²
ILL_IR	Illumination, wavelength > 700 nm				10	mW/cm²
RH	Relative Humidity (non-condensing)				95%

(1) Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected.

(2) All voltages are referenced to common ground VSS.

(3) VOFFSET supply transients must fall within specified max voltages.

(4) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit.

(5) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit. Refer to Power Supply Requirements for additional information.

(6) Tester Conditions for V_IH and V_IL:
Frequency = 60 MHz. Maximum Rise Time = 2.5 ns at (20% to 80%)
Frequency = 60 MHz. Maximum Fall Time = 2.5 ns at (80% to 20%)

(7) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tri-states the SCPDO output pin.

(8) The SCP clock is a gated clock. Duty cycle shall be 50% ± 10%. SCP parameter is related to the frequency of DCLK.

(9) SCP internal oscillator is specified to operate all SCP registers. For all SCP operations, DCLK is required.

(10) The DLP9000X, coupled with the DLPC910, is designed for operation at 2 specific DCLK frequencies only - 400 MHz or 480 MHz. 480 MHz operation is only allowed at the specific environmental operating conditions as shown in this table.

(11) Optimal, long-term performance and optical efficiency of the Digital Micromirror Device (DMD) can be affected by various application parameters, including illumination spectrum, illumination power density, micromirror landed duty-cycle, ambient temperature (storage and operating), DMD temperature, ambient humidity (storage and operating), and power on or off duty cycle. TI recommends that application-specific effects be considered as early as possible in the design cycle.

(12) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination will reduce device lifetime.

(13) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1) shown in Figure 15 and the package thermal resistance in Thermal Information using Micromirror Array Temperature Calculation.

(14) Per Figure 16, the maximum operational case temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. Refer to Micromirror Landed-On/Landed-Off Duty Cycle for a definition of micromirror landed duty cycle.

(15) Temperature delta is the highest difference between the ceramic test point (TP1) and window test points (TP2) and (TP3) in Figure 15.

(16) Refer to Thermal Information and Micromirror Array Temperature Calculation.

(17) Refer to Figure 1.

(18) Refer to Figure 2, Figure 3, and Figure 4.

(19) Long-term is defined as the usable life of the device.

(20) Array and Window temperatures beyond those specified as long-term are recommended for short-term conditions only (power-up). Short-term is defined as cumulative time over the usable life of the device and is less than 500 hours.

(21) For the DLP9000X, Figure 16 does not apply and the maximum temperature is as specified in table.

7.5 Thermal Information

THERMAL METRIC ⁽¹⁾		DLP9000	UNIT
		FLS (CLGA)
		355 PINS
R_θJA	Thermal resistance, active area to test point 1 (TP1) (max)	0.5	°C/W

(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package where it can be removed by an appropriate heat sink. The heat sink and cooling system must be capable of maintaining the package within the temperature range specified in the Recommended Operating Conditions. The total heat load on the DMD is largely driven by the incident light absorbed by the active area, although other contributions include light energy absorbed by the window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.

7.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS ⁽¹⁾	MIN	MAX	UNIT
V_OH	High-level output voltage	VCC = 3 V, I_OH = –20 mA	2.4		V
V_OL	Low level output voltage	VCC = 3.6, I_OL= 15 mA		0.4	V
I_IH	High–level input current ⁽²⁾ ⁽³⁾	VCC = 3.6 V, V_I = VCC		250	µA
IlL	Low level input current	VCC = 3.6 V, V_I = 0	–250		µA
I_OZ	High–impedance output current	VCC = 3.6 V		10	µA
CURRENT
I_CC	Supply current ⁽⁴⁾	DLP9000 VCC = 3.6 V, DCLK=400 MHz		1600	mA
I_CC		DLP9000X VCC = 3.6V, DCLK=480 MHz		1850
I_CCI		DLP9000 VCCI = 3.6 V, DCLK=400 MHz		985
I_CCI		DLP9000X VCCI = 3.6, DCLK=480 MHz		1100
I_OFFSET	Supply current ⁽⁵⁾	VOFFSET = 8.75 V		25	mA
I_BIAS	Supply current ⁽⁵⁾	VBIAS = 16.5 V		14	mA
I_RESET	Supply current	VRESET = –10.5 V		11	mA
I_TOTAL		DLP9000 Total Sum		2634
I_TOTAL		DLP9000X Total Sum		3000
POWER
P_CC	Supply power dissipation	DLP9000 VCC = 3.6 V		5760	mW
P_CC		DLP9000X VCC = 3.6 V		6660	mW
P_CCI		DLP9000 VCCI = 3.6 V		3546	mW
P_CCI		DLP9000X VCCI = 3.6 V		3960	mW
P_OFFSET		VOFFSET = 8.75 V		219	mW
P_BIAS		VBIAS = 16.5 V		231	mW
P_RESET		VRESET = –10.5 V		115	mW
P_TOTAL	Supply power dissipation ⁽⁶⁾	DLP9000 Total Sum, DCLK = 400 MHz		9871	mW
P_TOTAL	Supply power dissipation ⁽⁶⁾	DLP9000X Total Sum, DCLK = 480 MHz		11185	mW
CAPACITANCE
C_I	Input capacitance	ƒ = 1 MHz		10	pF
C_O	Output capacitance	ƒ = 1 MHz		10	pF
C_O	Reset group capacitance MBRST(31:0)	ƒ = 1 MHz; 2560 × 50 micromirrors	230	290	pF

(1) All voltages are referenced to common ground VSS. Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected.

(2) Applies to LVCMOS input pins only. Does not apply to LVDS pins and MBRST pins.

(3) LVCMOS input pins utilize an internal 18000 Ω passive resistor for pull-up and pull-down configurations. Refer to Pin Configuration and Functions to determine pull-up or pull-down configuration used.

(4) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit.

(5) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.

(6) Total power on the active micromirror array is the sum of the electrical power dissipation and the absorbed power from the illumination source. See the Micromirror Array Temperature Calculation.

7.7 Timing Requirements

over Recommended Operating Conditions (unless otherwise noted) ⁽¹⁾

				MIN	NOM	MAX	UNIT
SCP INTERFACE ⁽²⁾
t_r	Rise time	20% to 80%				200	ns
t_ƒ	Fall time	80% to 20%				200	ns
LVDS INTERFACE ⁽²⁾
t_r	Rise time	20% to 80%		100		400	ps
t_ƒ	Fall time	80% to 20%		100		400	ps
LVDS CLOCKS ⁽³⁾
t_c	Cycle time	DLP9000	DCLK_A, 50% to 50%	2.5			ns
			DCLK_B, 50% to 50%	2.5
			DCLK_C, 50% to 50%	2.5
			DCLK_D, 50% to 50%	2.5
		DLP9000X	DCLK_A, 50% to 50%	2.083
			DCLK_B, 50% to 50%	2.083
			DCLK_C, 50% to 50%	2.083
			DCLK_D, 50% to 50%	2.083
t_w	Pulse duration	DLP9000	DCLK_A, 50% to 50%	1.19	1.25		ns
			DCLK_B, 50% to 50%	1.19	1.25
			DCLK_C, 50% to 50%	1.19	1.25
			DCLK_D, 50% to 50%	1.19	1.25
		DLP9000X	DCLK_A, 50% to 50%	1.031	1.042
			DCLK_B, 50% to 50%	1.031	1.042
			DCLK_C, 50% to 50%	1.031	1.042
			DCLK_D, 50% to 50%	1.031	1.042
LVDS INTERFACE ⁽³⁾
t_su	Setup time	D_A(15:0) before rising or falling edge of DCLK_A		0.2			ns
		D_B(15:0) before rising or falling edge of DCLK_B		0.2
		D_C(15:0) before rising or falling edge of DCLK_C		0.2
		D_D(15:0) before rising or falling edge of DCLK_D		0.2
t_su	Setup time	SCTRL_A before rising or falling edge of DCLK_A		0.2			ns
		SCTRL_B before rising or falling edge of DCLK_B		0.2
		SCTRL_C before rising or falling edge of DCLK_C		0.2
		SCTRL_D before rising or falling edge of DCLK_D		0.2
t_h	Hold time	DLP9000	D_A(15:0) after rising or falling edge of DCLK_A	0.5			ns
			D_B(15:0) after rising or falling edge of DCLK_B	0.5
			D_C(15:0) after rising or falling edge of DCLK_C	0.5
			D_D(15:0) after rising or falling edge of DCLK_D	0.5
		DLP9000X	D_A(15:0) after rising or falling edge of DCLK_A	0.4
			D_B(15:0) after rising or falling edge of DCLK_B	0.4
			D_C(15:0) after rising or falling edge of DCLK_C	0.4
			D_D(15:0) after rising or falling edge of DCLK_D	0.4
t_h	Hold time	DLP9000	SCTRL_A after rising or falling edge of DCLK_A	0.5			ns
			SCTRL_B after rising or falling edge of DCLK_B	0.5
			SCTRL_C after rising or falling edge of DCLK_C	0.5
			SCTRL_D after rising or falling edge of DCLK_D	0.5
		DLP9000X	SCTRL_A after rising or falling edge of DCLK_A	0.4
			SCTRL_B after rising or falling edge of DCLK_B	0.4
			SCTRL_C after rising or falling edge of DCLK_C	0.4
			SCTRL_D after rising or falling edge of DCLK_D	0.4
LVDS INTERFACE ⁽³⁾
t_skew	Skew time	Channel B relative to Channel A	DLP9000 Channel A includes the following LVDS pairs: DCLK_AP and DCLK_AN SCTRL_AP and SCTRL_AN D_AP(15:0) and D_AN(15:0)	–1.25		1.25	ns
			DLP9000 Channel B includes the following LVDS pairs: DCLK_BP and DCLK_BN SCTRL_BP and SCTRL_BN D_BP(15:0) and D_BN(15:0)	–1.25		1.25	ns
			DLP9000X Channel A includes the following LVDS pairs: DCLK_AP and DCLK_AN SCTRL_AP and SCTRL_AN D_AP(15:0) and D_AN(15:0)	-1.04		1.04	ns
			DLP9000X Channel B includes the following LVDS pairs: DCLK_BP and DCLK_BN SCTRL_BP and SCTRL_BN D_BP(15:0) and D_BN(15:0)	-1.04		1.04	ns
		Channel D relative to Channel C	DLP9000 Channel C includes the following LVDS pairs: DCLK_CP and DCLK_CN SCTRL_CP and SCTRL_CN D_CP(15:0) and D_CN(15:0)	–1.25		1.25	ns
			DLP9000 Channel D includes the following LVDS pairs: DCLK_DP and DCLK_DN SCTRL_DP and SCTRL_DN D_DP(15:0) and D_DN(15:0)	–1.25		1.25	ns
			DLP9000X Channel C includes the following LVDS pairs: DCLK_CP and DCLK_CN SCTRL_CP and SCTRL_CN D_CP(15:0) and D_CN(15:0)	-1.04		1.04	ns
			DLP9000X Channel D includes the following LVDS pairs: DCLK_DP and DCLK_DN SCTRL_DP and SCTRL_DN D_DP(15:0) and D_DN(15:0)	-1.04		1.04	ns

(1) Refer to Pin Configuration and Functions for pin details.

(2) Refer to Figure 5.

(3) Refer to Figure 6.

Not to scale.

Refer to SCP Interface section of the Recommended Operating Conditions table.

Figure 1. SCP Timing Parameters

DLP9000 LVDS_Voltage_Definitions_references.gif

Refer to LVDS Interface section of the Recommended Operating Conditions table.

Refer to Pin Configuration and Functions for list of LVDS pins.

Figure 2. LVDS Voltage Definitions (References)

Not to scale.

Refer to LVDS Interface section of the Recommended Operating Conditions table.

Figure 3. LVDS Voltage Parameters

DLP9000 LVDS_Voltage_Definitions_Parameters.gif

Refer to LVDS Interface section of the Recommended Operating Conditions table.

Refer to Pin Configuration and Functions for list of LVDS pins.

Figure 4. LVDS Equivalent Input Circuit

Not to scale.

Refer to the Timing Requirements table

Refer to Pin Configuration and Functions for a list of LVDS pins and SCP pins..

Figure 5. Rise Time and Fall Time

Not to scale.

Refer to LVDS INTERFACE section in the Timing Requirements table.

Figure 6. Timing Requirement Parameter Definitions

Not to scale.

Refer to LVDS INTERFACE section in the Timing Requirements table.

Figure 7. LVDS Interface Channel Skew Definition

7.8 Capacitance at Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
C_I	Input capacitance	ƒ = 1 MHz		10	pF
C_O	Output capacitance	ƒ = 1 MHz		10	pF
C_IM	MBRST(31:0) input capacitance	f = 1 MHz. All inputs interconnected.	230	290	pF

7.9 Typical Characteristics

When the DLP9000 DMD is controlled by two DLPC900 controllers, these digital controllers offer four modes of operation.

Video Mode
Video Pattern Mode
Pre-Stored Pattern Mode
Pattern On-The-Fly Mode

In video mode, the video source is displayed on the DMD at the rate of the incoming video source.

In modes 2, 3, and 4, the pattern rates depend on the bit depth as shown in Table 1.

When the DLP9000X DMD is controlled by the DLPC910 controller, the digital controller offers streaming 1-bit binary patterns to the DMD at speeds greater than 61 Gigabits per second (Gbps). The patterns are streamed from a customer designed applications processor into the DLPC910 input LVDS data interface. Table 2 shows the pattern rates for the different DMD Reset Modes.

Table 1. DLPC900 with DLP9000 Pattern Rate versus Bit Depth

BIT DEPTH	VIDEO PATTERN MODE (Hz)	PRE-STORED or PATTERN ON-THE-FLY MODE (Hz)
1	2880	9523
2	1440	3289
3	960	2638
4	720	1364
5	480	823
6	480	672
7	360	500
8	247	247

Table 2. DLPC910 with DLP9000X Pattern Rates versus Reset Mode

RESET MODE⁽¹⁾	MAX PIXEL DATA RATE (Gbps)⁽²⁾	MAX PATTERN RATE (Hz) ⁽⁵⁾
Global	53.42	13043⁽³⁾
Single	56.46	13783 ⁽⁴⁾
Dual	59.89	14624 ⁽⁴⁾
Quad	61.39	14989⁽⁴⁾

(1) Refer to the DLPC910 data sheet in Related Documentation for a description of the reset modes.

(2) Pixel data rates are based on continuous streaming.

(3) Global reset mode allows for continuous or pulsed illumination source.

(4) This reset mode typically requires pulsed illumination such as a laser or LED.

(5) Increasing exposure periods may be necessary for a desired application but may decrease pattern rate.

7.10 System Mounting Interface Loads

PARAMETER		MAX	UNIT
Maximum system mounting interface load to be applied to the:	Thermal interface area (See Figure 8)	35	lbs
	Electrical interface area	300	lbs
	Datum A interface area ⁽¹⁾	160	lbs

(1) Combined loads of the thermal and electrical interface areas in excess of Datum “A” load shall be evenly distributed outside the Datum A area (300 + 35 – Datum A).

Figure 8. System Mounting Interface Loads

7.11 Micromirror Array Physical Characteristics

				VALUE	UNIT
M	Number of active columns		See Figure 9	2560	micromirrors
N	Number of active rows			1600	micromirrors
P	Micromirror (pixel) pitch			7.56	µm
	Micromirror active array width	M × P		19.3536	mm
	Micromirror active array height	N × P		12.096	mm
	Micromirror active border	Pond of micromirror (POM) ⁽¹⁾		14	micromirrors/ side
	Micromirror total area	P² x M x N (converted to cm)		2.341	cm²

(1) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM. These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical bias to tilt toward OFF.

Refer to section Micromirror Array Physical Characteristics table for M, N, and P specifications.

Figure 9. Micromirror Array Physical Characteristics

Figure 10. DMD Micromirror Active Area

7.12 Micromirror Array Optical Characteristics

Refer to Optical Interface and System Image Quality for important information.

PARAMETER		TEST CONDITIONS	MIN	NOM	MAX	UNIT
α	Micromirror tilt angle	DMD landed state ⁽¹⁾		12		°
β	Micromirror tilt angle tolerance ⁽¹⁾ ⁽²⁾ ⁽³⁾ ⁽⁴⁾ ⁽⁵⁾		–1		1	°
	Micromirror tilt direction ⁽⁵⁾ ⁽⁶⁾	See Figure 11	44	45	46	°
	Number of out-of-specification micromirrors ⁽⁷⁾	Adjacent micromirrors			0	micromirrors
	Number of out-of-specification micromirrors ⁽⁷⁾	Non-adjacent micromirrors			10	micromirrors
	Micromirror crossover time ⁽⁸⁾ ⁽⁹⁾	Typical performance		2.5		μs
	DMD efficiency within the wavelength range 400 nm to 420 nm ⁽¹⁰⁾			68%
	DMD photopic efficiency within the wavelength range 420 nm to 700 nm ⁽¹⁰⁾			66%

(1) Measured relative to the plane formed by the overall micromirror array.

(2) Additional variation exists between the micromirror array and the package datums.

(3) Represents the landed tilt angle variation relative to the nominal landed tilt angle.

(4) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different devices.

(5) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result in colorimetry variations, system efficiency variations, or system contrast variations.

(6) When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON State direction. A binary value of 0 results in a micromirror landing in the OFF State direction.

(7) An out-of-specification micromirror is defined as a micromirror that is unable to transition between the two landed states within the specified Micromirror Switching Time.

(8) Micromirror crossover time is primarily a function of the natural response time of the micromirrors.

(9) Performance as measured at the start of life.

(10) Efficiency numbers assume 24-degree illumination angle, F/2.4 illumination and collection cones, uniform source spectrum, and uniform pupil illumination. Efficiency numbers assume 100% electronic mirror duty cycle and do not include optical overfill loss. Note that this number is specified under conditions described above and deviations from the specified conditions could result in decreased efficiency.

DLP9000 Micromirror_Landed_Orientation.gif

Refer to section Micromirror Array Physical Characteristics table for M, N, and P specifications.

Figure 11. Micromirror Landed Orientation and Tilt

7.13 Optical and System Image Quality

Optimizing system optical performance and image quality strongly relate to optical system design parameter trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical performance is contingent on compliance to the optical system operating conditions described in a) through c) below:

Numerical Aperture and Stray Light Control. The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the projection lens. The mirror tilt angle defines DMD capability to separate the "ON" optical path from any other light path, including undesirable flat-state specular reflections from the DMD window, DMD border structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the mirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger than the illumination numerical aperture angle, objectionable artifacts in the display’s border and/or active area could occur.
Pupil Match. TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally centered within two degrees of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable artifacts in the display’s border and/or active area, which may require additional system apertures to control, especially if the numerical aperture of the system exceeds the pixel tilt angle.
Illumination Overfill. Overfill light illuminating the area outside the active array can create artifacts from the mechanical features that surround the active array and other surface anomalies that may be visible on the screen. The illumination optical system should be designed to limit light flux incident anywhere outside the active array more than 20 pixels from the edge of the active array on all sides. Depending on the particular system’s optical architecture and assembly tolerances, this amount of overfill light on the outside of the active array may still cause artifacts to still be visible.

NOTE

TI ASSUMES NO RESPONSIBILITY FOR IMAGE QUALITY ARTIFACTS OR DMD FAILURES CAUSED BY OPTICAL SYSTEM OPERATING CONDITIONS EXCEEDING LIMITS DESCRIBED ABOVE.

7.14 Window Characteristics

PARAMETER ⁽¹⁾	TEST CONDITIONS	MIN	TYP
Window material designation	Corning 7056
Window refractive index	at wavelength 589 nm		1.487
Window aperture	See ⁽²⁾
Illumination overfill	Refer to Illumination Overfill
Window transmittance, single–pass through both surfaces and glass ⁽³⁾	At wavelength 405 nm. Applies to 0° and 24° AOI only.	95%
	Minimum within the wavelength range 420 nm to 680 nm. Applies to all angles 0° to 30° AOI.	97%
	Average over the wavelength range 420 nm to 680 nm. Applies to all angles 30° to 45° AOI.	97%

(1) Refer to Window Characteristics and Optics for more information.

(2) For details regarding the size and location of the window aperture, refer to the package mechanical characteristics listed in the Mechanical ICD in the Mechanical, Packaging, and Orderable Information section.

(3) Refer to the TI application report DLPA031, Wavelength Transmittance Considerations for DMD Window.

7.15 Chipset Component Usage Specification

The DMD is a component of one or more DLP® chipsets. Reliable function and operation of the DMD requires that it be used in conjunction with the other components of the applicable DLP chipset, including those components that contain or implement TI DMD control technology. TI DMD control technology is the TI technology and devices for operating or controlling a DMD.