10.1.1 Printed Circuit Board Design Guidelines

The PCB design may vary depending on system design. Table 14 provides general recommendations on the PCB design.

10.1.2 Printed Circuit Board Layer Stackup Geometry

The PCB layer stack may vary depending on system design. However, careful attention is required in order to meet design considerations listed in the following sections. Table 15 provides general guidelines for the mDDR and DMD interface stackup geometry.

10.1.3 Signal Layers

The PCB signal layers should follow these recommendations:

• Layer changes should be minimized for single-ended signals.
• Individual differential pairs can be routed on different layers, but the signals of a given pair should not change layers.
• Stubs should be avoided.
• Only voltage or low-frequency signals should be routed on the outer layers, except as noted previously in this document.
• Double data rate signals should be routed first.

10.1.4 Routing Constraints

In order to meet the specifications listed in Table 16 and Table 17, typically the PCB designer must route these signals manually (not using automated PCB routing software). In case of length matching requirements, the longer signals should be routed in a serpentine fashion, keeping the number of turns to a minimum and the turn angles no sharper than 45 degrees. Avoid routing long traces all around the PCB.

Each high-speed, single-ended signal must be routed in relation to its reference signal, such that a constant impedance is maintained throughout the routed trace. Avoid sharp turns and layer switching while keeping lengths to a minimum. The following signals should follow these signal matching requirements.

10.1.5 Termination Requirements

Table 18 lists the termination requirements for the DMD and mDDR interfaces.

For applications where the routed distance of the mDDR or DMD signal can be kept less than 0.75 inches, then this signal is short enough not to be considered a transmission line and should not need a series terminating resistor.

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10.1.6 PLL

The DLPC300 contains one internal PLL that has a dedicated analog supply (VDD_PLL, VSS_PLL). As a minimum, the VDD_PLL power and VSS_PLL ground pins should be isolated using an RC-filter consisting of two 50-Ω series ferrites and two shunt capacitors (to widen the spectrum of noise absorption). TI recommends that one capacitor be a 0.1-µF capacitor and the other be a 0.01-µF capacitor. All four components should be placed as close to the controller as possible, but it is especially important to keep the leads of the high-frequency capacitors as short as possible. Note that both capacitors should be connected across VDD_PLL and VSS_PLL on the controller side of the ferrites.

The PCB layout is critical to PLL performance. It is vital that the quiet ground and power are treated like analog signals. Therefore, VDD_PLL must be a single trace from the DLPC300 to both capacitors and then through the series ferrites to the power source. The power and ground traces should be as short as possible, parallel to each other and as close as possible to each other. See Figure 20.

10.1.7 General Handling Guidelines for Unused CMOS-Type Pins

To avoid potentially damaging current caused by floating CMOS input-only pins, TI recommends that unused controller input pins be tied through a pullup resistor to its associated power supply or through a pulldown to ground. For controller inputs with internal pullup or pulldown resistors, it is unnecessary to add an external pullup/pulldown unless specifically recommended. Note that internal pullup and pulldown resistors are weak and should not be expected to drive the external line. The DLPC300 implements very few internal resistors and these are noted in the pin list.

Unused output-only pins can be left open.

When possible, TI recommends that unused bidirectional I/O pins be configured to their output state such that the pin can be left open. If this control is not available and the pins may become an input, then they should be pulled up (or pulled down) using an appropriate resistor.

10.1.8 Hot-Plug Usage

Note that the DLPC300 provides fail-safe I/O on all host-interface signals (signals powered by VCC_INTF). This allows these inputs to be driven high even when no I/O power is applied. Under this condition, the DLPC300 does not load the input signal nor draw excessive current that could degrade controller reliability. Thus, for example, the I²C bus from the host to other components would not be affected by powering off VCC_INTF to the DLPC300. Note that TI recommends weak pullups or pulldowns on signals feeding back to the host to avoid floating inputs.

10.1.9 External Clock Input Crystal Oscillator

The DLPC300 requires an external reference clock to feed its internal PLL. This reference may be supplied via a crystal or oscillator. The DLPC300 accepts a reference clock of 16.667 MHz with a maximum frequency variation of 200 ppm (including aging, temperature, and trim component variation). When a crystal is used, several discrete components are also required as shown in Figure 19.

A. CL = Crystal load capacitance (Farads)

B. CL1 = 2 × (CL – Cstray_pll_refclk_i)

C. CL2 = 2 × (CL – Cstray_pll_refclk_o)

D. Where

• Cstray_pll_refclk_i = Sum of package and PCB stray capacitance at the crystal pin associated with the ASIC pin pll_refclk_i.
• Cstray_pll_refclk_o = Sum of package and PCB stray capacitance at the crystal pin associated with the ASIC pin pll_refclk_o.

Figure 19. Recommended Crystal Oscillator Configuration

If an external oscillator is used, then the oscillator output must drive the PLL_REFCLK_I pin on the DLPC300 controller, and the PLL_REFCLK_O pins should be left unconnected. The benefit of an oscillator is that it can be made to provide a spread-spectrum clock that reduces EMI. However, the DLPC300 can only accept between 0% to –2% spreading (that is, down spreading only) with a modulation frequency between 20 and 65 kHz and a triangular waveform.

Similar to the crystal option, the oscillator input frequency is limited to 16.667 MHz.

It is assumed that the external crystal or oscillator stabilizes within 50 ms after stable power is applied.

Table 19 contains the recommended crystal configuration parameters.

Table 20. Driver Board PCB Stackup and Impedance⁽¹⁾