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ZHCS244C January 2012 – August 2015 DLPC300

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DLPC300 controller enables integration of the DLP3000 WVGA chipset into small-form-factor and low-cost light steering applications. Example end equipments for the 0.3 WVGA chipset include 3D scanning or metrology systems with structured light, interactive displays, chemical analyzers, medical instruments, and other end equipments requiring spatial light modulation (or light steering and patterning).

8.2 Typical Application

The DLPC300 is one of the two devices in the DLP3000 WVGA chipset (see Figure 14). The other device is the DLP3000 DMD. For proper operation of the chipset, the DLPC300 requires a serial flash device with configuration information. This information is loaded after RESET is released. The configuration information is available for download from the DLPR300 product folder.

Figure 14. Chipset Block Diagram

8.2.1 Design Requirements

The DLP3000 WVGA chipset consists of two individual components:

DLP3000 – 0.3 WVGA series 220 DMD
DLPC300 – DLP3000 controller

Plus two additional components:

SPI serial configuration flash loaded with the DLPC300 Configuration and Support Firmware
Mobile DDR SDRAM

Detailed specifications for the components can be found in the individual component data sheets.

Figure 14 illustrates the connectivity between the individual components in the chipset, which include the following internal chipset interfaces:

DLPC300 to DLP3000 data and control interface (DMD pattern data)
DLPC300 to DLP3000 micromirror array reset control interface
DLPC300 to mobile DDR SDRAM
DLPC300 to SPI serial flash

Figure 15 illustrates the connectivity between the chipset and other key system-level components, which include the following external chipset interfaces:

Data Interface, consisting of:
- 24-bit data bus (PDATA[23:0])
- Vertical sync signal (VSYNC)
- Horizontal sync signal (HSYNC)
- Data valid signal (DATAEN)
- Data clock signal (PCLK)
- Data mask (PDM)
Control Interface, consisting of:
- I²C signals (SCL and SDA)
- Park signal (PARK)
- Reset signal (RESET)
- Oscillator signals (PLL_REFCLK)
- Mobile DDR SDRAM interface (mDDR)
- Serial configuration flash interface
- Illumination driver control interface

8.2.2 Detailed Design Procedure

8.2.2.1 System Input Interfaces

The DLP3000 WVGA Chipset supports a single 24-bit parallel RGB interface for data transfers from another device. The system input also requires that proper configuration of the PARK and RESETinputs to ensure reliable operation.

See Specifications for further details on each of the following interfaces.

8.2.2.1.1 Control Interface

The DLP3000 WVGA chipset supports I²C commands to control its operation. The control interface allows another master processor to send commands to the DLP3000 WVGA chipset to configure the chipset, query system status or perform real-time operations, such as set the LED drive current or display splash screens stored in serial flash memory. The DLPC300 offers two different slave addresses. The I2C_ADDR_SEL pin provides the ability to select an alternate set of 7-bit I²C slave address. If I2C_ADDR_SEL is low, then the DLPC300 slave address is 1Bh. If I2C-ADDR_SEL pin is high, then the DLPC300 slave address is 1Dh. See the DLPC300 Programmer's Guide (DLPU004) for detailed information about these operations.

Table 2 provides a description for active signals used by the DLPC300 to support the I²C interface.

Table 2. Active Signals – I²C Interface

SIGNAL NAME	DESCRIPTION
SCL	I²C clock. Bidirectional open-drain signal
SDA	I²C data. Bidirectional open-drain signal

8.2.2.2 Input Data Interface

The data Interface is a digital video input port with up to 24-bit RGB, and has a nominal I/O voltage of 3.3 V. The data interface also supports a 24-bit BT656 video interface. As shown in Figure 15 (system block diagram), the data Interface can be configured to connect to an external processor or a video decoder device through an 8-, 16-, 18-, or 24-bit parallel interface.

Table 3 provides a description of the signals associated with the data interface.

Table 3. Active Signals – Data Interface

SIGNAL NAME	DESCRIPTION
PDATA(23:0)	24-bit data inputs (8 bits for each of the red, green, and blue channels)
PCLK	Pixel clock; all input signals on data interface are synchronized with this clock.
VSYNC	Vertical sync
HSYNC	Horizontal sync
DATAEN	Input data valid
PDM	Parallel data mask

Maximum and minimum input timing specifications are provided in Parallel Interface Frame Timing Requirements and Parallel Interface General Timing Requirements. The mapping of the red-, green-, and blue-channel data bits is shown in Figure 12.

8.2.2.3 System Output Interfaces

There are two primary output interfaces: illumination driver control interface and sync outputs.

8.2.2.3.1 Illumination Interface

An illumination interface is provided that supports up to a three (3) channel LED driver.

The illumination interface provides signals that support: LED driver enable, LED enable, LED enable select, and PWM signals to control the LED current.

Table 4 describes the active signals for the illumination interface.

Table 4. Active Signals – Illumination Interface

SIGNAL NAME	DESCRIPTION
LED_ENABLE	LED enable
LEDDRV_ON	LED driver master enable
LED_SEL(1:0)	Red, Green, or Blue LED enable select
RED_EN	Red LED enable
GREEN_EN	Green LED enable
BLUE_EN	Blue LED enable
RPWM	Red LED PWM signal used to control the LED current
GPWM	Green LED PWM signal used to control the LED current
BPWM	Blue LED PWM signal used to control the LED current

8.2.2.4 System Support Interfaces

8.2.2.4.1 Mobile DDR Synchronous Dram (MDDR)

The DLP3000 WVGA chipset relies on the use of mobile DDR SDRAM to store DMD formatted patterns. The SDRAM interface is a 16-bit wide bus and nominally operates at a frequency of 166 MHz. The data bus is routed in a point-to-point fashion between the DLPC300 and the mDDR devices, where each data line only makes a single connection between the DLPC300 and the mDDR device.

Listed below are the compatibility requirements for the mDDR:

SDRAM memory Type: Mobile DDR

Size: 128 M-bit minimum. DLPC300 can only address 128 Mb . Use of larger memories requires bit A13 to be grounded

Organization: N x 16-bits wide with 4 equally sized banks

Burst Length: 4

Refresh period: ≥ 64 ms

Speed Grade t_CK: 6 ns max

CAS Latency (C_L): 3 clocks

t_RCD: 3 clocks

t_RP: 3 clocks

Table 5 describes the signals for the SDRAM interface.

Table 5. Active Signals – Mobile DDR Synchronous Dram (MDDR)

SIGNAL NAME	DESCRIPTION
MEM_A(12:0)	13-bit address bus
MEM_BA(1:0)	Bank select signals
MEM_CKE	Clock enable
MEM_CAS	Column address strobe
MEM_RAS	Row address strobe
MEM_CS	Chip select
MEM_WE	Write enable
MEM_LDQS	R/W data strobe for lower byte
MEM_LDM	Write data mask for lower byte
MEM_UDQS	R/W data strobe for upper byte
MEM_UDM	Write data mask for upper byte
MEM_DQ(15:0)	16-bit data bus
MEM_CLK_N	Negative signal of the differential clock pair
MEM_CLK_P	Positive signal of the differential clock pair

Table 6 shows the mDDR DRAM devices recommended for use with the DLPC300.

Table 6. Compatible MDDR Dram Device Options⁽¹⁾⁽⁴⁾

Vendor	Part Number⁽²⁾	Size	Organization	Speed Grade⁽³⁾ (t_CK)	CAS Latency (C_L) t_RCD, t_RP Parameters (Clocks)
Elpida	EDD25163HBH-6ELS-F⁽⁵⁾	256 Mb	16M × 16	6 ns	3, 3, 3
Samsung	K4X56163PN-FGC6⁽⁵⁾	256 Mb	16M × 16	6 ns	3, 3, 3
Micron	MT46H16M16LFBF-6IT:H	256 Mb	16M × 16	6 ns	3, 3, 3
Micron	MT46H32M16LF-6 IT:B	512 MB	32M × 16	6 ns	3, 3, 3
Micron	MT46H32M16LFBF-6:B	512 MB	32M × 16	6 ns	3, 3, 3
Micron	MT46H64M16LFCK-5:A⁽⁵⁾	1 Gb	64M × 16	6 ns	3, 3, 3
Hynix	H5MS2562JFR-J3M	256 Mb	16M × 16	6 ns	3, 3, 3
Winbond	W947D6HBHX6E	128 Mb	8M × 16	6 ns	3, 3, 3

(1) All the SDRAM devices listed have been verified to be compatible with the DLPC300.

(2) These part numbers reflect a Pb-free package.

(3) A 6-ns speed grade corresponds to a 166-MHz mDDR device.

(4) The DLPC300 does not use partial-array self-refresh or temperature-compensated self-refresh options.

(5) These devices are EOL and should not be used in new designs.

8.2.2.4.2 Flash Memory Interface

DLPC300 uses an external 16-Mb SPI serial flash slave memory device for configuration support. The contents of this flash memory can be downloaded from the DLPC300 product folder. The DLPC300 uses a single SPI interface, employing SPI mode 0 protocol, operating at a nominal frequency of 33.3 MHz.

When RESET is released, the DLPC300 reads the contents of the serial flash memory and executes an auto-initialization routine. During this time, INIT_DONE is set high to indicate auto-initialization is busy. Upon completion of the auto-initialization routine, the DLPC300 sets INIT_DONE low to indicate that the auto-initialization routine successfully completed.

The DLPC300 should support any flash device that is compatible with standard SPI mode 0 protocol and meet the timing requirement shown in Flash Interface Timing Requirements. However, the DLPC300 does not support the normal (slow) read opcode, and thus cannot automatically adapt protocol and clock rate based on the electronic signature ID of the flash. The flash instead uses a fixed SPI clock and assumes certain attributes of the flash have been ensured by PCB design. The DLPC300 also assumes the flash supports address auto-incrementing for all read operations. Table 7 lists the specific Instruction opcode and timing compatibility requirements for a DLPC300-compatible flash.

Table 7. SPI Flash Instruction Opcode and Timing Compatibility Requirements

SPI Flash Command	Opcode (hex)	Address Bytes	Dummy Bytes	Clock Rate
Fast READ (single output)	0x0B	3	1	33.3 MHz
All others	Can vary	Can vary	Can vary	33.3 MHz

The DLPC300 does not have any specific page, block or sector size requirements except that programming through the I²C interface requires the use of page-mode programming. However, if the user would like to dedicate a portion of the serial flash for storing external data (such as calibration data) and access it through the DLPC300's I²C interface, then the minimum sector size must be considered, as it drives minimum erase size.

Note that the DLPC300 does not drive the HOLD (active-low hold) or WP (active-low write protect) pins on the flash device, and thus these pins should be tied to a logic high on the PCB by an external pullup.

The DLPC300 supports 1.8-, 2.5-, or 3.3-V serial flash devices. To do so, VCC_FLSH must be supplied with the corresponding voltage.

Table 8 describes the signals used to support this interface.

Table 8. Active Signals – DLPC300 Serial Configuration Flash Prom

SIGNAL NAME	DESCRIPTION
SPIDOUT	Serial configuration flash data output (from DLPC300 to flash)
SPIDIN	Serial configuration flash data input (from flash to DLPC300)
SPICLK	Serial configuration flash clock
SPICS0	Serial configuration flash chip select

Table 9 contains a list of 1.8-, 2.5-, and 3.3-V compatible SPI serial flash devices supported by DLPC300.

Table 9. Compatible SPI Flash Device Options⁽¹⁾

Density	Vendor	Part Number⁽²⁾	Supply Voltage Supported⁽³⁾	Min Chip Select High Time (t_CSH)	Max Fast Read FREQ⁽⁴⁾	Compatible With OpCode and Timing in Table 7
4 Mb	Macronix	MX25U4035	1.65 V–2 V	30 ns	40 MHz	Yes
8 Mb	Macronix	MX25U8035	1.65 V–2 V	30 ns	40 MHz	Yes
16 Mb	Winbond	W25Q16BLxxxx	2.3 V–3.6 V	100 ns	50 MHz	Yes
8 Mb	Macronix	MX25L8005ZUx-xxG	2.7 V–3.6 V	100 ns	66 MHz	Yes

(1) All the SPI devices listed have been verified to be compatible with DLPC300.

(2) Lower case x is used as a wildcard placeholder and indicates an option that is selectable by the user. Note that the use of an upper case X is part of the actual part number.

(3) The flash supply voltage must match VCC_FLSH on the DLPC300. 1.8-V and 2.5-V SPI device options are limited. Take care when ordering devices to be sure the desired supply voltage is attained, as multiple voltage options are often available under the same base part number.

(4) Maximum supported fast read frequency at the minimum supported supply voltage

8.2.2.4.3 DLPC300 Reference Clock

The DLPC300 requires a 16.667-MHz 1.8-V external input from an oscillator. This signal is the DLP3000 WVGA chipset reference clock from which the majority of the interfaces derive their timing. This includes mDDR SDRAM, DMD interfaces, and serial interfaces.

See Specifications for reference clock specifications.

8.2.2.5 DMD Interfaces

8.2.2.5.1 DLPC300 to DLP3000 Digital Data

The DLPC300 provides the DMD pattern data to the DMD over a double data rate (DDR) interface.

Table 10 describes the signals used for this interface.

Table 10. Active Signals – DLPC300 to DLP3000 Digital Data Interface

DLPC300 SIGNAL NAME	DLP3000 SIGNAL NAME
DMD_D(14:0)	DATA(14:0)
DMD_DCLK	DCLK

8.2.2.5.2 DLPC300 to DLP3000 Control Interface

The DLPC300 provides the control data to the DMD over a serial bus.

Table 11 describes the signals used for this interface.

Table 11. Active Signals – DLPC300 to DLP3000 Control Interface

DLPC300 SIGNAL NAME	DLP3000 SIGNAL NAME	DESCRIPTION
DMD_SAC_BUS	SAC_BUS	DMD stepped-address control (SAC) bus data
DMD_SAC_CLK	SAC_CLK	DMD stepped-address control (SAC) bus clock
DMD_LOADB	LOADB	DMD data load signal
DMD_SCTRL	SCTRL	DMD data serial control signal
DMD_TRC	TRC	DMD data toggle rate control

8.2.2.5.3 DLPC300 to DLP3000 Micromirror Reset Control Interface

The DLPC300 controls the micromirror clock pulses in a manner to ensure proper and reliable operation of the DMD.

Table 12 describes the signals used for this interface.

Table 12. Active Signals – DLPC300-to-DLP3000 Micromirror Reset Control Interface

DLPC300 SIGNAL NAME	DLP3000 SIGNAL NAME	DESCRIPTION
DMD_DRC_BUS	DRC_BUS	DMD reset control serial bus
DMD_DRC_OE	DRC_OE	DMD reset control output enable
DMD_DRC_STRB	DRC_STRB	DMD reset control strobe

8.2.2.6 Maximum Signal Transition Time

Unless otherwise noted, 10 ns is the maximum recommended 20% to 80% rise/fall time to avoid input buffer oscillation. This applies to all DLPC300 input signals. However, the PARK input signal includes an additional small digital filter that ignores any input-buffer transitions caused by a slower rise or fall time for up to 150 ns.

8.3 System Examples

8.3.1 Video Source System Application

Figure 15 shows a typical embedded system application using the DLPC300. In this configuration, the DLPC300 controller supports a 24-bit parallel RGB, typical of LCD interfaces, from the main processor chip. This system supports both still and motion video sources. For this configuration, the controller only supports periodic sources. This is ideal for motion video sources, but can also be used for still images by maintaining periodic syncs but only sending a frame of data when needed. The still image must be fully contained within a single video frame and meet frame timing constraints. The DLPC300 refreshes the displayed image at the source frame rate and repeats the last active frame for intervals in which no new frame has been received.

Figure 15. Typical Embedded System Block Diagram

8.3.2 High Pattern Rate System With Optional Fpga

An optional FPGA (see the DLPR300 software folder) can be added to the system to manage the bit-planes stored in the mDDR. The mDDR accommodates four 608 × 684 images of 24-bit RGB data or 96 bit-planes (24 bit-planes × 4 images). By preloading the mDDR with these bit-planes, faster frame rates can be achieved. The 96 bit-plane buffer is arranged in a circular buffer style, meaning that the last bit-plane addition to the buffer replaces the oldest stored bit-plane. Figure 16 shows the overall system with the optional FPGA.

Figure 16. DLP3000 Chipset with Optional FPGA

With this FPGA, the pattern frame rate can be calculated with Equation 1.

Equation 1. DLPC300 Pattern_Rate_Equation.gif

where

Typical first bit plane load time = 215 µs
Typical buffer rotate overhead = 135 µs

Table 13 shows the maximum pattern rate that can be achieved by using a single FPGA internal buffer in continuous mode.

Table 13. Maximum Pattern Rate with Optional FPGA

Color Mode		Maximum Number of Patterns	Maximum Pattern Rate
Monochrome	1 bit per pixel	96	4000 Hz
	2 bits per pixel	48	1100 Hz
	3 bits per pixel	32	590 Hz
	4 bits per pixel	24	550 Hz
	5 bits per pixel	16	450 Hz
	6 bits per pixel	16	365 Hz
	7 bits per pixel	12	210 Hz
	8 bits per pixel	12	115 Hz

The digital RGB input interface operates at 1.8 V, 2.5 V, or 3.3 V nominal, depending on the VCC_INTF supply. The SPI flash interface operates at 1.8 V, 2.5 V, or 3.3 V nominal, depending on the VCC_FLSH supply. The DMD and mDDR interface operates at 1.8 V nominal (VCC18). The core transistors operate at 1 V nominal (VDD10). The analog PLL operates at 1 V nominal (VDD_PLL).