The DLPC910 interface is made up of several buses and controls signals as shown in the following list. The LVDS input buses provide the means of loading data to the DLPC910. The LVDS output buses provide the data to the DMD. Each input and output LVDS bus has an associated clock which clocks the data into the DLPC910 or into the DMD. Row and Block control signals define the type of mirror clock pulse to use after all the data is loaded into the DMD. Refer to Table 7-11 to obtain the required LVDS buses for each DMD supported.

• LVDS differential inputs
  • DDC_DCLK 4 buses
  • DVALID 4 buses
  • DDC_DIN 4 buses

• LVDS differential outputs. Refer to LVDS Output Bus Skew for recommendations on trace lengths.
  • DDC_DOUT 4 buses
  • DDC_DCLKOUT 4 buses
  • DDC_SCTRL 4 buses

• Control output signals
  • DMD RESET
  • DMD SCP

• Row and Block control input signals
  • ROWMD
  • ROWAD
  • BLKMD
  • BLKAD
  • RST2BLKZ

• Control input signals
  • COMP_DATA
  • NS_FLIP
  • WDT_ENBLZ
  • PWR_FLOAT
  • LOAD4_ENZ

• Status output signals
  • RST_ACTIVE
  • INIT_ACTIVE
  • ECP2_FINISHED
  • DMD_IRQ

• Controller reset
  • CTRL_RSTZ

• DLPR910 interface
  • PGM(4:0)
  • JTAG(3:0)