The data clock interface consists of four differential pairs: DDC_DCLK_A, DDC_DCLK_B, DDC_DCLK_C, and DDC_DCLK_D. Each must operate continuously. All signals associated with the data clock should be synchronous to these signals. For example, DDC_DIN_A and DVALID_A should be synchronous to the rising edge of DDC_DCLK_A. This clock should be valid prior to releasing CTRL_RSTZ. DDC_DCLK is a DDR clock with data loaded on both rising and falling edges of DDC_DCLK. The jitter on this clock is specified in Timing Requirements. When connecting the DLPC910 with a DLP6500, SPEED_SEL[1:0] inputs must be set to "00".