The DMD incorporates block clear operations using the BLKMD and BLKAD signals as shown in Table 7-12. The block address does not automatically increment and must be set to the desired block to be cleared. The Block clear operation writes logic zero data to all the SRAM cells in one DMD block regardless of the COMP_DATA input state. It is not possible to clear a DMD block while writing to a different block. BLKMD and BLKAD are asserted to perform a MCP on the block(s) that have been cleared. The customer interface should introduce a delay on the last block(s) that were issued a MCP to allow the mirrors to become stable. Each Block Clear operation must be followed by two no-op row load cycles. For the DLP9000X/DLP9000XUV there are 16 total Block Clear commands and 32 total no-op row cycles that are required to clear the entire DMD array. For the DLP6500 there are 15 total Block Clear commands and 30 total no-op row cycles that are required to clear the entire DMD array.