The DMD data is loaded one row at a time with the LVDS buses into the DMD SRAM array. All DMD data buses are required for correct operation. Refer to Table 7-11 to obtain the required LVDS buses for each DMD supported. Each bus consists of a differential clock (DDC_DCLKOUT), a differential control signal (DDC_SCTRL), and 16 differential pairs of LVDS signals (DDC_DOUT[15:0]) that are output from the DLPC910. Data and control are clocked into the DMD on both the rising and falling edges of the DDC_DCLKOUT clocks. Data loading does not cause mirror switching until a MCP operation is completed.

The number of clocks to load a row can be calculated as:

where

• C = number of clocks per row
• P = number of pixels per row
• D = data bus bit width
• E = 2. (Data is clocked on both the rising and falling edge of DCLK.)

Example:
C = 2560 / (64 × 2) = 20 clocks per row

Row address orientation depends on the North or South Flip Flag (NS_FLIP) input to the DLPC910. Refer to Related Documentation for the DMD datasheet regarding orientation of rows, columns, and MCP blocks. The row address counter does not automatically wrap-around when using the increment row address pointer instruction. After the final row is addressed, the row address pointer must be cleared to 0.