9.2.2 Detailed Design Procedure

When creating a new system design with an Ethernet PHY, follow this schematic capture procedure:

1. Select desired PHY hardware configurations in Table 18.
2. Use the Electrical Characteristics table and Table 17 to select the correct external bootstrap resistors.
3. If using LEDs, ensure the correct external circuit is applied as shown in Figure 28.
4. Select an appropriate clock source that adheres to either the CMOS-level oscillator or crystal resonator requirements within the Electrical Characteristics table.
5. Select a CMC, a list of recommended CMCs are located in Table 129.
6. Add common-mode termination, DC-blocking capacitors, an MDI-coupling capacitor, and an ESD shunt found in Table 128.
7. Ensure that there is sufficient supply decoupling on VDDIO and VDDA supply pins.
8. Add an external pullup resistor (tie to VDDIO) on MDIO line.
9. If sleep modes are not desired, WAKE and EN pins should be tied to VDDIO directly or through an external pullup resistor.

The following layout procedure should be followed:

1. Locate the PHY near the edge of the board so that short MDI traces can be routed to the desired connector.
2. Place the MDI external components: CMC, DC-blocking capacitors, CM termination, MDI-coupling capacitor, and ESD shunt.
3. Create a top-layer metal pour keepout under the CMC.
4. Ensure that the MDI TRD_M and TRD_P traces are routed such that they are 100-Ω differential.
5. Place the clock source near the XI and XO pins.
6. Ensure that when configured for MII, RMII, or RGMII operation, the xMII pins are routed 50-Ω and are single-ended with reference to ground.
7. Ensure that transmit path xMII pins are routed such that setup and hold timing does not violate the PHY requirements.
8. Ensure that receive path xMII pins are routed such that setup and hold timing does not violate the MAC requirements.
9. Place the MDIO pullup close to the PHY.