For more details about features and additional description information on the device Universal Asynchronous Receiver Transmitter, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.
Table 7-81 represents UART timing conditions.
Table 7-81 UART Timing Conditions
| PARAMETER |
DESCRIPTION |
MIN |
MAX |
UNIT |
| Input Conditions |
| tSR |
Input slew rate |
0.5 |
5 |
V/ns |
| Output Conditions |
| CLOAD |
Output load capacitance |
1 |
30(1) |
pF |
(1) This value represents an absolute maximum load capacitance. As the UART baud
rate increases, it may be necessary to reduce the load capacitance to a value
less than this maximum limit to provide enough timing margin for the attached
device. The output rise/fall times increase as capacitive load increases, which
decreases the time data is valid for the receiver of the attached devices.
Therefore, it is important to understand the minimum data valid time required by
the attached device at the operating baud rate. Then use the device IBIS models
to verify the actual load capacitance on the UART signals does not increase the
rise/fall times beyond the point where the minimum data valid time of the
attached device is violated.
Section 7.9.5.21.1, Section 7.9.5.21.2, and Figure 7-111 present timing requirements and switching characteristics for UART interface.