The half-bridge drivers can be controlled in two modes to support control schemes with either PWM input pins or SPI register control. The half-bridge drivers also have configuration registers (HB_OUT_CNFG1 and HB_OUT_CNFG2) to enable half-bridge control and to set up control mode (PWM or SPI).

The half-bridges can be configured for control by input signal from either PWM1 or IPROPI/PWM2 pins. The signal to PWM1 pin can be multiplexed internally to half-bridges, high-side drivers, and heater driver. IPROPI/PWM control from PWM2 pin is only available for half-bridges. When IPROPI/PWM2 pin is configured for PWM input, IPROPI sense output becomes unavailable.

IPROPI/PWM2 is sense output by default. The configuration table is shown below. Note that OUT5 and OUT6 are configured in HB_OUT_CNFG2 and OUT1 through OUT4 are configured in HB_OUT_CNFG1:

When the half-bridges are configured for SPI register control (OUTx_CNFG = 01b), the half-bridges high- and low-side MOSFETs can be individually controlled in register GD_HB_CTRL with bits OUTx_CTRL. The control truth table for the half-bridge outputs is shown below:

The half-bridge control mode can be changed anytime SPI communication is available by writing to the bits. This change is immediately reflected.

When the half-bridges are configured for PWM operation (OUTx_CNFG = 01Xb or 10Xb), the inputs can accept static or pulse-width modulated (PWM) voltage signals for either 100% or PWM drive modes. The default behavior for half-bridges during off-state of PWM signal is to Hi-Z the output.

The device automatically generates the dead-time needed during transitioning between the high-side and low-side FET on the switching half-bridge. This timing is based on internal FET gate-source voltage voltage. No external timing is required. This scheme ensures minimum dead time, while guaranteeing no shoot-through current.