In H-bridge control, both half-bridge gate drivers can be controlled as an H-bridge gate driver through a configurable combination of IN1 and IN2 input pins or the S_IN1 and S_IN2 bits in registerGD_HB_CTRL.

To set the control mode for the half-bridge gate drivers, the SPI BRG_MODE bit can be configured to either PH/EN or PWM control modes. The PH/EN mode allows for the H-bridge to be controlled with a speed/direction type of interface commanded by one PWM signal and one GPIO signal. The PWM mode allows for the H-bridge to be controlled with a more advanced scheme typically requiring two PWM signals. This allows the H-bridge driver to enter four different output states for additional control flexibility if required.

In PH/EN mode, each half-bridge input control modes are configured with bits INx_MODE in register GD_CNFG. By default, INx_MODE = 0b and both half-bridge are controlled from pins. If INx_MODE = 1b, the half-bridge is controlled with SPI bit S_INx. If IN1_MODE is set to 1b and IN2_MODE is set to 0b, the half-bridge 1 is controlled through SPI bit S_IN1, and half-bridge 2 is controlled with pin IN2. If both INx_MODE = 1b, then S_IN1 becomes EN and S_IN2 becomes PH, following pins IN1 and IN2.

The H-bridge freewheeling state is configurable through the BRG_FW register setting. In both the PH/EN and PWM modes the default active freewheeling mode is active low-side. This setting can be utilized to modify the bridge between low-side or high-side active freewheeling.

The H-bridge can be set to the Hi-Z state through the PWM or PH/EN control mode, using DRVOFF pin or S_HIZx bits. The S_HIZx bits are an OR when the gate driver is in PH/EN control mode, and puts both outputs SHx into high impedance.

Figure 7-20 H-Bridge PH/EN Control

Figure 7-21 H-Bridge PH/EN Mixed Control

Figure 7-22 H-Bridge PH/EN Control (BRG_MODE = 01b, IN1_MODE = 1b)

Figure 7-23 H-Bridge PWM Control