When the device is active and waiting for drive commands (nSLEEP is HI), there is an open-load detection loop for half-bridges OUT1 - OUT6. The detection scheme sequentially checks the open-load status for each high- and low-side of each half-bridge output and reports the status in bit OUTx_OLA in register HB_STAT2 and WARN bit in register IC_STAT1.

From standby or sleep mode, starting with OUT1, the control loop will begin to check open-load status. The open-load detection threshold is configurable for either 32 or 128 cycles with bit OUTx_OLA_TH in register HB_OL_CNFG2. If an output is driven with EN/DIS only (no PWM switching) then the open-load detection time is 5 ms.

If open-load is detected for longer than the cycle count threshold or before timeout occurs, then bit OUTx_OLA is reported. If no open-load is detected after 32 or 128 cycles, then the loop moves to the next half-bridge. The loop continues checking each output through OUT6, then goes back to OUT1 to restart the OLA loop. For the open-load check to be valid, the half-bridge open-load detection must be enabled (OUTx_OLA = 1b) and the output must be enabled (OUTx_CNFG = X1b). The diagram below shows the OLA scheme:

Any given half-bridge is skipped if any of the following three conditions are met:

1. OUTx is disabled (OUTx_CNFG = 00b).
2. Open-load detect is not enabled (OUTx_OLA = 0b) for the half-bridge.
3. OUTx is OFF for more than 5ms
4. OLA has already been detected and flagged, or other fault condition on OUTx (overcurrent, over temperature)

With all half-bridge OUTx enabled without PWM, the total loop time can take up to 46 ms to cycle through all half-bridges. When a half-bridge is driven individually or sequentially, the loop detects open load within 5 ms or faster (depending on EN or PWM control). If a half-bridge is driven with a low frequency external PWM signal, the OFF time of the output can exceed the open-load detection window of 5 ms, and so the half-bridge is skipped.