If the voltage across the V_DS overcurrent comparator exceeds the V_{DS_LVL} for longer than the t_{DS_DG} time, a V_DS overcurrent condition is detected. The voltage threshold and deglitch time can be adjusted through the or and VDS_DG register settings.

The V_DS overcurrent monitor can respond and recover in four different modes set through the VDS_MODE register setting.

• Latched Fault Mode: After detecting the overcurrent event, the gate driver pull downs are enabled and FAULT register bit, and associated VDS register bit are asserted. After the overcurrent event is removed, the fault state remains latched until CLR_FLT is issued.
• Cycle by Cycle Mode: After detecting the overcurrent event, the gate driver pull downs are enabled and FAULT register bit, and associated VDS_XX register bit are asserted. The next PWM input will clear the FAULT register bit and reenable the driver automatically. The associated VDS_XX register bit will remain asserted until CLR_FLT is issued.
• Warning Report Only Mode: The overcurrent event is reported in the WARN and associated VDS_XX register bits. The device will not take any action. The warning remains latched until CLR_FLT is issued.
• Disabled Mode: The V_DS overcurrent monitors are disabled and will not respond or report.

When a V_DS overcurrent fault occurs, the gate pull down current can be configured in order to increase or decrease the time to disable the external MOSFET. This can help to avoid a slow-turn off during high-current short circuit conditions. This setting is configure through the VDS_IDRVN register setting.