ZHCSJ76A March   2018  – April 2019 DRV8343-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     简化原理图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions—DRV8343H
    2.     Pin Functions—DRV8343S
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Three Phase Smart Gate Drivers
        1. 8.3.1.1 PWM Control Modes
          1. 8.3.1.1.1 6x PWM Mode (PWM_MODE = 000b or MODE Pin Tied to AGND)
          2. 8.3.1.1.2 3x PWM Mode (PWM_MODE = 001b or MODE Pin = 18 kΩ to AGND)
          3. 8.3.1.1.3 1x PWM Mode (PWM_MODE = 010b or MODE Pin = 75 kΩ to AGND)
          4. 8.3.1.1.4 Independent Half-Bridge PWM Mode (PWM_MODE = 011b or MODE Pin is > 1.5 MΩ to AGND or Hi-Z)
          5. 8.3.1.1.5 Phases A and B are Independent Half-Bridges, Phase C is Independent FET (MODE = 100b)
          6. 8.3.1.1.6 Phases B and C are Independent Half-Bridges, Phase A is Independent FET (MODE = 101b or MODE Pin is 75 kΩ to DVDD)
          7. 8.3.1.1.7 Phases A is Independent Half-Bridge, Phases B and C are Independent FET (MODE = 110b or MODE Pin is 18 kΩ to DVDD)
          8. 8.3.1.1.8 Independent MOSFET Drive Mode (PWM_MODE = 111b or MODE Pin = 0.47 kΩ to DVDD)
        2. 8.3.1.2 Device Interface Modes
          1. 8.3.1.2.1 Serial Peripheral Interface (SPI)
          2. 8.3.1.2.2 Hardware Interface
        3. 8.3.1.3 Gate Driver Voltage Supplies
        4. 8.3.1.4 Smart Gate Drive Architecture
          1. 8.3.1.4.1 IDRIVE: MOSFET Slew-Rate Control
          2. 8.3.1.4.2 TDRIVE: MOSFET Gate Drive Control
          3. 8.3.1.4.3 Propagation Delay
          4. 8.3.1.4.4 MOSFET VDS Monitors
          5. 8.3.1.4.5 VDRAIN Sense Pin
          6. 8.3.1.4.6 nFAULT Pin
      2. 8.3.2 DVDD Linear Voltage Regulator
      3. 8.3.3 Pin Diagrams
      4. 8.3.4 Low-Side Current Sense Amplifiers
        1. 8.3.4.1 Bidirectional Current Sense Operation
        2. 8.3.4.2 Unidirectional Current Sense Operation (SPI only)
        3. 8.3.4.3 Amplifier Calibration Modes
        4. 8.3.4.4 MOSFET VDS Sense Mode (SPI Only)
      5. 8.3.5 Gate Driver Protective Circuits
        1. 8.3.5.1  VM Supply Undervoltage Lockout (UVLO)
        2. 8.3.5.2  VCP Charge Pump Undervoltage Lockout (CPUV)
        3. 8.3.5.3  MOSFET VDS Overcurrent Protection (VDS_OCP)
          1. 8.3.5.3.1 VDS Latched Shutdown (OCP_MODE = 00b)
          2. 8.3.5.3.2 VDS Automatic Retry (OCP_MODE = 01b)
          3. 8.3.5.3.3 VDS Report Only (OCP_MODE = 10b)
          4. 8.3.5.3.4 VDS Disabled (OCP_MODE = 11b)
        4. 8.3.5.4  VSENSE Overcurrent Protection (SEN_OCP)
          1. 8.3.5.4.1 VSENSE Latched Shutdown (OCP_MODE = 00b)
          2. 8.3.5.4.2 VSENSE Automatic Retry (OCP_MODE = 01b)
          3. 8.3.5.4.3 VSENSE Report Only (OCP_MODE = 10b)
          4. 8.3.5.4.4 VSENSE Disabled (OCP_MODE = 11b)
        5. 8.3.5.5  Gate Driver Fault (GDF)
        6. 8.3.5.6  Thermal Warning (OTW)
        7. 8.3.5.7  Thermal Shutdown (OTSD)
          1. 8.3.5.7.1 Latched Shutdown (OTSD_MODE = 0b)
          2. 8.3.5.7.2 Automatic Recovery (OTSD_MODE = 1b)
        8. 8.3.5.8  Open Load Detection (OLD)
          1. 8.3.5.8.1 Open Load Detection in Passive Mode (OLP)
            1. 8.3.5.8.1.1 OLP Steps
          2. 8.3.5.8.2 Open Load Detection in Active Mode (OLA)
        9. 8.3.5.9  Offline Shorts Diagnostics
          1. 8.3.5.9.1 Offline Short-to-Supply Diagnostic (SHT_BAT)
          2. 8.3.5.9.2 Offline Short-to-Ground Diagnostic (SHT_GND)
        10. 8.3.5.10 Reverse Supply Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Gate Driver Functional Modes
        1. 8.4.1.1 Sleep Mode
        2. 8.4.1.2 Operating Mode
        3. 8.4.1.3 Fault Reset (CLR_FLT or ENABLE Reset Pulse)
    5. 8.5 Programming
      1. 8.5.1 SPI Communication
        1. 8.5.1.1 SPI
          1. 8.5.1.1.1 SPI Format
    6. 8.6 Register Maps
      1. 8.6.1 Status Registers
        1. 8.6.1.1 FAULT Status Register (Address = 0x00) [reset = 0x00]
          1. Table 16. FAULT Status Register Field Descriptions
        2. 8.6.1.2 DIAG Status A Register (Address = 0x01) [reset = 0x00]
          1. Table 17. DIAG Status A Register Field Descriptions
        3. 8.6.1.3 DIAG Status B Register (Address = 0x02) [reset = 0x00]
          1. Table 18. DIAG Status B Register Field Descriptions
        4. 8.6.1.4 DIAG Status C Register (address = 0x03) [reset = 0x00]
          1. Table 19. DIAG Status C Register Field Descriptions
      2. 8.6.2 Control Registers
        1. 8.6.2.1  IC1 Control Register (Address = 0x04) [reset = 0x00]
          1. Table 21. IC1 Control Field Descriptions
        2. 8.6.2.2  IC2 Control Register (address = 0x05) [reset = 0x40]
          1. Table 22. IC2 Control Field Descriptions
        3. 8.6.2.3  IC3 Control Register (Address = 0x06) [reset = 0xFF]
          1. Table 23. IC3 Control Field Descriptions
        4. 8.6.2.4  IC4 Control Register (Address = 0x07) [reset = 0xFF]
          1. Table 24. IC4 Control Field Descriptions
        5. 8.6.2.5  IC5 Control Register (Address = 0x08) [reset = 0xFF]
          1. Table 25. IC5 Control Field Descriptions
        6. 8.6.2.6  IC6 Control Register (Address = 0x09) [reset = 0x99]
          1. Table 26. IC6 Control Field Descriptions
        7. 8.6.2.7  IC7 Control Register (Address = 0x0A) [reset = 0x99]
          1. Table 27. IC7 Control Field Descriptions
        8. 8.6.2.8  IC8 Control Register (Address = 0x0B) [reset = 0x99]
          1. Table 28. IC8 Control Field Descriptions
        9. 8.6.2.9  IC9 Control Register (Address = 0x0C) [reset = 0x2F]
          1. Table 29. IC9 Control Field Descriptions
        10. 8.6.2.10 IC10 Control Register (Address = 0x0D) [reset = 0x61]
          1. Table 30. IC10 Control Field Descriptions
        11. 8.6.2.11 IC11 Control Register (Address = 0x0E) [reset = 0x00]
          1. Table 31. IC11 Control Field Descriptions
        12. 8.6.2.12 IC12 Control Register (Address = 0x0F) [reset = 0x2A]
          1. Table 32. IC12 Control Field Descriptions
        13. 8.6.2.13 IC13 Control Register (Address = 0x10) [reset = 0x7F]
          1. Table 33. IC13 Control Field Descriptions
        14. 8.6.2.14 IC14 Control Register (Address = 0x10) [reset = 0x00]
          1. Table 34. IC14 Control Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Primary Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 External MOSFET Support
            1. 9.2.1.2.1.1 Example
          2. 9.2.1.2.2 IDRIVE Configuration
            1. 9.2.1.2.2.1 Example
          3. 9.2.1.2.3 VDS Overcurrent Monitor Configuration
            1. 9.2.1.2.3.1 Example
          4. 9.2.1.2.4 Sense Amplifier Bidirectional Configuration
            1. 9.2.1.2.4.1 Example
          5. 9.2.1.2.5 External Components
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Application With One Sense Amplifier
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Sense Amplifier Unidirectional Configuration
            1. 9.2.2.2.1.1 Example
            2. 9.2.2.2.1.2 Unused pins
          2. 9.2.2.2.2 External Components
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Consideration in Generator Mode
    2. 10.2 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 器件命名规则
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5 Electrical Characteristics

Over recommended operating conditions 5.5 ≤ VVM ≤ 60 V (unless otherwise noted). Typical limits apply for  VVM = 24 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (DVDD, VCP, VM)
IVM VM operating supply current VVM = 24 V, ENABLE = 3.3 V, INHx/INLx = 0 V, SHx = 0 V 12 16 mA
IVMQ VM sleep mode supply current ENABLE = 0 V, VVM = 24 V, TA = 25°C 12 20 µA
ENABLE = 0 V, VVM = 24 V, TA = 125°C 50
tRST Reset pulse time ENABLE = 0 V period to reset faults 4.4 43 µs
tWAKE(1) Turnon time ENABLE = 3.3 V to outputs ready, VVM > VUVLO 1 ms
tSLEEP Turnoff time ENABLE = 0 V to device sleep mode 1 ms
VDVDD DVDD regulator voltage VVM > 6 V, IDVDD = 0 to 30 mA 3 3.3 3.6 V
VVM = 5.5 to 6 V, IDVDD = 0 to 20 mA 3 3.3 3.6 V
VVCP VCP operating voltage
with respect to VM		 VVM = 13 V, IVCP = 0 to 25 mA 8.4 11 12.5 V
VVM = 10 V, IVCP = 0 to 20 mA 6.3 9 10
VVM = 8 V, IVCP = 0 to 15 mA 5.4 7 8
VVM = 5.5 V, IVCP = 0 to 5 mA 4 5 6
LOGIC-LEVEL INPUTS (CAL, ENABLE, INHx, INLx, SCLK, SDI)
VIL Input logic low voltage 0 0.7 V
VIH Input logic high voltage 1.6 5.5 V
VHYS Input logic hysteresis 182 mV
IIL Input logic low current VVIN = 0 V; INHx, INLx, SDI(IDRIVE), SCLK(VDS), ENABLE –5 5 µA
IIH Input logic high current VVIN = 5 V; INHx, INLx, SDI(IDRIVE), SCLK(VDS) 50 90 µA
IIH Input logic high current VVIN = 5 V; ENABLE 80 110 µA
RPD Pulldown resistance To AGND; INHx, INLx, SDI(IDRIVE), SCLK(VDS) 50 100 200 kΩ
RPD Pulldown resistance To AGND; ENABLE 30 60 110 kΩ
tPD Propagation delay INHx/INLx input buffer and digital core propagation delay.  Dead time is  excluded. 105 ns
LOGIC LEVEL INPUT (nSCS)
VIL,nSCS Input logic low voltage 0 0.7 V
VIH,nSCS Input logic high voltage 1.6 5.5 V
RPU,nSCS Pullup resistance To DVDD 25 50 90 kΩ
FOUR-LEVEL H/W INPUT (GAIN)
VI1 Input mode 1 voltage Tied to AGND 0 V
VI2 Input mode 2 voltage 47 kΩ ± 5% to tied AGND 1.2 V
VI3 Input mode 3 voltage Hi-Z ( > 500 kΩ to AGND) 2 V
VI4 Input mode 4 voltage Tied to DVDD 3.3 V
RPU Pullup resistance Internal pullup to DVDD 25 50 80 kΩ
RPD Pulldown resistance Internal pulldown to AGND 40 84 130 kΩ
SEVEN-LEVEL H/W INPUTS (MODE, IDRIVE, VDS)
VI1 Input mode 1 voltage Tied to AGND 0 V
VI2 Input mode 2 voltage 18 kΩ ± 5% tied to AGND 0.5 V
VI3 Input mode 3 voltage 75 kΩ ± 5% tied to AGND 1.1 V
VI4 Input mode 4 voltage Hi-Z ( > 1.5 MΩ ) 1.65 V
VI5 Input mode 5 voltage 75 kΩ ± 5% tied to DVDD 2.2 V
VI6 Input mode 6 voltage 18 kΩ ± 5% tied to DVDD 2.8 V
VI7 Input mode 7 voltage MODE : 0.47 kΩ ± 5% tied to DVDD 
VDS, IDRIVE : Tied to DVDD		 3.3 V
RPU Pullup resistance Internal pullup to DVDD 35 73 125 kΩ
RPD Pulldown resistance Internal pulldown to AGND 35 73 125 kΩ
PUSH-PULL OUTPUT (SDO)
RPU,SDO Internal pullup To VSDO = 5 V 40 90 Ω
To VSDO = 3.3 V 60 120
RPD,SDO Internal pulldown To GND 30 50 Ω
OPEN DRAIN OUTPUT (nFAULT)
VOL Output logic low voltage IO = 5 mA 0.15 V
IOZ Output high impedance leakage VO = 5 V –1 9 µA
GATE DRIVERS (GHx, GLx)
VGSH  High-side gate drive voltage
with respect to SHx		 VVM = 13 V, IVCP = 0 to 25 mA, GHx no output load 8.4 11 12.5 V
VVM = 10 , IVCP = 0 to 20 mA, GHx no output load 6.3 9 10
VVM = 8 V, IVCP = 0 to 15 mA, GHx no output load 5.4 7 8
VVM = 5.5 V, IVCP = 0 to 5 mA, GHx no output load 4 5 6
VGSL Low-side gate drive voltage
with respect to PGND		 VVM = 12 V, IVCP = 0 to 25 mA, GLx no output load 9 11 12 V
VVM = 10 V, IVCP = 0 to 20 mA, GLx no output load 9.9 10.0 10.1
VVM = 8 V, IVCP = 0 to 15 mA, GLx no output load 7.9 8.0 8.1
VVM = 5.5 V, IVCP = 0 to 5 mA, GLx no output load 5.4 5.5 5.6
tDEAD Gate drive
dead time		 SPI Device DEAD_TIME = 00b 500 ns
DEAD_TIME = 01b 1000
DEAD_TIME = 10b 2000
DEAD_TIME = 11b 4000
H/W Device 1000
tDRIVE Peak current
gate drive time		 SPI Device TDRIVE = 00b 500 ns
TDRIVE = 01b 1000
TDRIVE = 10b 2000
TDRIVE = 11b 3000
H/W Device 3000
tDRIVE_MAX Peak current gate drive max time IDRIVEP_Hx = 0000b, 0001b, 0010b, 0011b 20 µs
IDRIVEP Peak source
gate current		 SPI Device IDRIVEP_Hx  = 0000b (GHx), VVM = 24 V 0.45 1.5 3.0 mA
IDRIVEP_Lx = 0000b (GLx), VVM = 24 V 0.81 2.7 5.4
IDRIVEP_Hx =  0001b (GHx), VVM = 24 V 1.05 3.5 7
IDRIVEP_Lx = 0001b (GLx), VVM = 24 V 1.17 3.9 7.8
IDRIVEP_Hx = 0010b (GHx), VVM = 24 V 1.5 5 10
IDRIVEP_Lx = 0010b (GLx), VVM = 24 V 1.95 6.5 13
IDRIVEP_Hx or IDRIVEP_Lx = 0011b (GHx/GLx), VVM = 24 V 3 10 20
IDRIVEP_Hx or IDRIVEP_Lx = 0100b (GHx/GLx), VVM = 24 V 4.5 15 30
IDRIVEP_Hx or IDRIVEP_Lx = 0101b (GHx/GLx), VVM = 24 V 15 50 100
IDRIVEP_Hx or IDRIVEP_Lx = 0110b (GHx/GLx), VVM = 24 V 18 60 120
IDRIVEP_Hx or IDRIVEP_Lx = 0111b (GHx/GLx), VVM = 24 V 19.5 65 130
IDRIVEP_Hx or IDRIVEP_Lx = 1000b (GHx/GLx), VVM = 24 V 76 200 400
IDRIVEP_Hx or IDRIVEP_Lx = 1001b (GHx/GLx), VVM = 24 V 79.8 210 420
IDRIVEP_Hx or IDRIVEP_Lx = 1010b (GHx/GLx), VVM = 24 V 98.8 260 520
IDRIVEP_Hx or IDRIVEP_Lx = 1011b (GHx/GLx), VVM = 24 V 100.7 265 530
IDRIVEP_Hx or IDRIVEP_Lx = 1100b (GHx/GLx), VVM = 24 V 279.3 735 1470
IDRIVEP_Hx or IDRIVEP_Lx = 1101b (GHx/GLx), VVM = 24 V 304 800 1600
IDRIVEP_Hx or IDRIVEP_Lx = 1110b (GHx/GLx), VVM = 24 V 355.3 935 1870
IDRIVEP_Hx or IDRIVEP_Lx = 1111b (GHx/GLx), VVM = 24 V 380 1000 2000
H/W Device IDRIVE = Tied to AGND (GHx), VVM = 24 V 0.45 1.5 3.0
IDRIVE = Tied to AGND (GLx), VVM = 24 V 0.81 2.7 5.4
IDRIVE = 18 kΩ ± 5% tied to AGND (GHx), VVM = 24 V 1.5 5 10
IDRIVE = 18 kΩ ± 5% tied to AGND (GLx), VVM = 24 V 1.95 6.5 13
IDRIVE = 75 kΩ ± 5% tied to AGND (GHx/GLx), VVM = 24 V 3 10 20
IDRIVE = Hi-Z (GHx/GLx), VVM = 24 V 18 60 120
IDRIVE = 75 kΩ ± 5% tied to DVDD (GHx/GLx), VVM = 24 V 76 200 400
IDRIVE = 18 kΩ ± 5% tied to DVDD (GHx/GLx), VVM = 24 V 98.8 260 520
IDRIVE = Tied to DVDD (GHx/GLx), VVM = 24 V 380 1000 2000
IDRIVEN Peak sink
gate current		 SPI Device IDRIVEN_Hx or IDRIVEN_Lx = 0000b, VVM = 24 V 0.9 3 5.4 mA
IDRIVEN_Hx or IDRIVEN_Lx = 0001b, VVM = 24 V 2.09 7 12.6
IDRIVEN_Hx or IDRIVEN_Lx = 0010b, VVM = 24 V 3 10 18
IDRIVEN_Hx or IDRIVEN_Lx = 0011b, VVM = 24 V 6 20 36
IDRIVEN_Hx or IDRIVEN_Lx= 0100b, VVM = 24 V 9 30 54
IDRIVEN_Hx or IDRIVEN_Lx = 0101b, VVM = 24 V 30 100 180
IDRIVEN_Hx or IDRIVEN_Lx = 0110b, VVM = 24 V 36 120 216
IDRIVEN_Hx or IDRIVEN_Lx = 0111b, VVM = 24 V 39 130 234
IDRIVEN_Hx or IDRIVEN_Lx = 1000b, VVM = 24 V 120 400 720
IDRIVEN_Hx or IDRIVEN_Lx = 1001b, VVM = 24 V 126 420 756
IDRIVEN_Hx or IDRIVEN_Lx = 1010b, VVM = 24 V 156 520 936
IDRIVEN_Hx or IDRIVEN_Lx = 1011b, VVM = 24 V 159 530 954
IDRIVEN_Hx or IDRIVEN_Lx = 1100b, VVM = 24 V 441 1470 2646
IDRIVEN_Hx or IDRIVEN_Lx = 1101b, VVM = 24 V 480 1600 2880
IDRIVEN_Hx or IDRIVEN_Lx = 1110b, VVM = 24 V 561 1870 3366
IDRIVEN_Hx or IDRIVEN_Lx = 1111b, VVM = 24 V 600 2000 3600
H/W Device IDRIVE = Tied to AGND, VVM = 24 V 0.9 3 5.4
IDRIVE = 18 kΩ ± 5% tied to AGND, VVM = 24 V 3 10 18
IDRIVE = 75 kΩ ± 5% tied to AGND, VVM = 24 V 6 20 36
IDRIVE = Hi-Z, VVM = 24 V 36 120 216
IDRIVE = 75 kΩ ± 5% tied to DVDD, VVM = 24 V 120 400 720
IDRIVE = 18 kΩ ± 5% tied to DVDD, VVM = 24 V 156 520 936
IDRIVE = Tied to DVDD, VVM = 24 V 600 2000 3600
IHOLDP Gate holding source current after tDRIVE SPI Device IDRIVEP_Hx = 0000b, VVM = 24 V 0.45 1.5 3.8 mA
IDRIVEP_Hx = 0001b, VVM = 24 V 1.05 3.5 7
IDRIVEP_Hx = 0010b, VVM = 24 V 1.5 5 10
IDRIVEP_Hx = 0011b, VVM = 24 V 3 10 20
All other IDRIVE settings, VVM = 24 V 4.5 15 30
H/W Device IDRIVE tied to AGND, VVM = 24 V 0.45 1.5 3.8
IDRIVE = 18 kΩ ± 5% tied to AGND, VVM = 24 V 1.5 5 10
IDRIVE = 75 kΩ ± 5% tied to AGND, VVM = 24 V 3 10 20
All other IDRIVE settings, VVM = 24 V 4.5 15 30
IHOLDN Gate holding sink current after tDRIVE SPI Device IDRIVEP_Hx = 0000b, VVM = 24 V 0.9 3 5.4 mA
IDRIVEP_Hx = 0001b, VVM = 24 V 2 7 12.6
IDRIVEP_Hx = 0010b, VVM = 24 V 3 10 18
IDRIVEP_Hx = 0011b, VVM = 24 V 6 20 36
All other IDRIVE settings, VVM = 24 V 9 30 54
H/W Device IDRIVE tied to AGND, VVM = 24 V 0.9 3 5.4
IDRIVE = 18 kΩ ± 5% tied to AGND, VVM = 24 V 3 10 18
IDRIVE = 75 kΩ ± 5% tied to AGND, VVM = 24 V 6 20 36
All other IDRIVE settings, VVM = 24 V 9 30 54
ISTRONG Gate strong pulldown current 
(GHx to SHx and GLx to PGND)		 IDRIVEP_Hx = 0000b, 0001b, 0010b, 0011b, VVM = 24 V 9 30 54 mA
All other IDRIVE settings, VVM = 24 V 0.6 2 3.6 A
ROFF Gate hold off resistor GHx to SHx 150 280 kΩ
ROFF Gate hold off resistor GLx to PGND 150 280 kΩ
CURRENT SHUNT AMPLIFIER (SNx, SOx, SPx, VREF)
GCSA Amplifier gain SPI Device CSA_GAIN = 00b, CSA_FET = 0b 4.9 5 5.1 V/V
CSA_GAIN = 01b, CSA_FET = 0b 9.8 10 10.2
CSA_GAIN = 10b, CSA_FET = 0b 19.6 20 20.4
CSA_GAIN = 11b, CSA_FET = 0b 39.2 40 40.8
SPI Device  CSA_GAIN = 00b, CSA_FET = 1b 4.85 5 5.15
CSA_GAIN = 01b, CSA_FET = 1b 9.7 10 10.3
CSA_GAIN = 10b, CSA_FET = 1b 19.4 20 20.6
CSA_GAIN = 11b, CSA_FET = 1b 38.8 40 41.2
H/W Device GAIN = Tied to AGND 4.9 5 5.1
GAIN = 47 kΩ ± 5% tied to AGND 9.8 10 10.2
GAIN = Hi-Z 19.6 20 20.4
GAIN = Tied to DVDD 39.2 40 40.8
tSET Settling time to ±1% VO_STEP = 0.5 V, GCSA = 5 V/V 150 ns
VO_STEP = 0.5 V, GCSA = 10 V/V 300
VO_STEP = 0.5 V, GVSA = 20 V/V 600
VO_STEP = 0.5 V, GCSA = 40 V/V 1200
VCOM Common mode input range –0.15 0.15 V
VDIFF Differential mode input range –0.3 0.3 V
VOFF Input offset error VSP = VSN = 0 V,  VREF = 3.3 V,  GCSA = 10, 20, 40 V/V –4 4 mV
VOFF Input offset error VSP = VSN = 0 V,  VREF = 3.3 V, GCSA = 5 V/V –5 5 mV
VDRIFT Drift offset VSP = VSN = 0 V -45 10 45 µV/°C
VLINEAR SOx output voltage linear range 0.25 VVREF – 0.25 V
VBIAS SOx output voltage bias SPI Device VSP = VSN = 0 V, CAL = 3.3 V, VREF_DIV = 0b VVREF – 0.3 V
VSP = VSN = 0 V, CAL = 3.3 V, VREF_DIV = 1b VVREF / 2
H/W Device VSP = VSN = 0 V, CAL = 3.3 V VVREF / 2
IBIAS SPx/SNx input bias current 100 µA
VSLEW SOx output slew rate 60-pF load 10 V/µs
IVREF VREF input current VVREF = 5 V 2 3 mA
UGB Unity gain bandwidth 60-pF load 8 MHz
PROTECTION CIRCUITS
VUVLO VM undervoltage lockout VM falling, UVLO report 5.2 5.4 V
VM rising, UVLO recovery 5.4 5.9
VUVLO,DVDD DVDD undervoltage lockout 2.9 V
VUVLO_HYS VM undervoltage hysteresis Rising to falling threshold 200 mV
tUVLO_DEG VM undervoltage deglitch time VM falling, UVLO report 11.5 µs
VCPUV Charge pump undervoltage lockout VCP falling, CPUV report VVM + 1.4 VVM + 2.5 VVM + 3.1 V
VGS_CLAMP High-side gate clamp Positive clamping voltage 15 16.5 19 V
Negative clamping voltage –0.7
VOLA Open load active mode detection threshold DLx – VDRAIN 150 300 430 mV
SLx – SHx, –1 < SLx < 0 150 300 500
IOL Open load current 2.5 mA
tOLP Open load passive diagnostic delay SPI Device OLP_SHRT_DLY = 00b 0.25 ms
OLP_SHRT_DLY = 01b 1.25
OLP_SHRT_DLY = 10b 5
OLP_SHRT_DLY = 11b 11.5
H/W Device After tWAKE and tSHORTS elapse 5
tSHORTS Offline short-to-battery and short-to-GND diagnostic delay SPI Device OLP_SHRT_DLY = 00b 0.1 ms
OLP_SHRT_DLY = 01b 0.5
OLP_SHRT_DLY = 10b 2
OLP_SHRT_DLY = 11b 4.4
H/W Device After tWAKE elapses 2
VVDS_OCP VDS overcurrent
trip voltage		 SPI Device VDS_LVL = 0000b 0.01 0.06 0.11 V
VDS_LVL = 0001b 0.08 0.13 0.18
VDS_LVL = 0010b 0.15 0.2 0.25
VDS_LVL = 0011b 0.2 0.26 0.32
VDS_LVL = 0100b 0.24 0.31 0.38
VDS_LVL = 0101b 0.38 0.45 0.52
VDS_LVL = 0110b 0.45 0.53 0.61
VDS_LVL = 0111b 0.51 0.6 0.69
VDS_LVL = 1000b 0.59 0.68 0.77
VDS_LVL = 1001b 0.64 0.75 0.86
VDS_LVL = 1010b 0.81 0.94 1.07
VDS_LVL = 1011b 0.97 1.13 1.29
VDS_LVL = 1100b 1.14 1.3 1.46
VDS_LVL = 1101b 1.34 1.5 1.66
VDS_LVL = 1110b 1.52 1.7 1.88
VDS_LVL = 1111b 1.69 1.88 2.07
H/W Device VDS = Tied to AGND 0.01 0.06 0.11
VDS = 18 kΩ ± 5% tied to AGND 0.08 0.13 0.18
VDS = 75 kΩ ± 5% tied to AGND 0.2 0.26 0.32
VDS = Hi-Z 0.51 0.6 0.69
VDS = 75 kΩ ± 5% tied to DVDD 0.97 1.13 1.29
VDS = 18 kΩ ± 5% tied to DVDD 1.69 1.88 2.07
VDS = Tied to DVDD Disabled
tOCP_DEG VDS and VSENSE overcurrent deglitch time SPI Device OCP_DEG=000b 2.5 µs
OCP_DEG = 001b 4.75
OCP_DEG = 010b 6.75
OCP_DEG = 011b 8.75
OCP_DEG = 100b 10.25
OCP_DEG = 101b 11.5
OCP_DEG = 110b 16.5
OCP_DEG = 111b 20.5
H/W Device 4.75
VSEN_OCP VSENSE overcurrent trip voltage SPI Device SEN_LVL = 00b 0.25 V
SEN_LVL = 01b 0.5
SEN_LVL = 10b 0.75
SEN_LVL = 11b 1
H/W Device 1
tRETRY Overcurrent fault retry time SPI Device TRETRY = 00b 2 ms
TRERTY = 01b 4
TRETRY = 10b 6
TRETRY = 11b 8
THYS Thermal hysteresis Die temperature, TJ 20 °C
TOTSD Thermal shutdown temperature Die temperature, TJ 150 170 188 °C
TOTW Thermal warning temperature Die temperature, TJ 130 150 169 °C
(1) Does not include OLP/Shorts diagnostic delay time in the H/W device
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