8.3.3 Pin Diagrams

Figure 25 shows the input structure for the logic level pins, INHx, INLx, CAL, ENABLE, nSCS, SCLK, and SDI. The input can be driven with a voltage or external resistor.

Figure 25. Logic-Level Input Pin Structure

Figure 26 shows the structure of the four level input pin, GAIN, on hardware interface devices. The input can be set with an external resistor.

Figure 26. Four Level Input Pin Structure

Figure 27 shows the structure of the seven level input pins, MODE, IDRIVE and VDS, on hardware interface devices. The input can be set with an external resistor.

Figure 27. Seven Level Input Pin Structure ⁽¹⁾

1. V_I7 requires a 0.47 kΩ resistor to DVDD for MODE input pin. VDS and IDRIVE pins can be directly tied to DVDD.

Figure 28 shows the structure of the open-drain output pin, nFAULT. The open-drain output requires an external pullup resistor to function correctly.

Figure 28. Open-Drain Output Pin Structure