ZHCSR67 July 2020 DRV8353M
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Absolute Maximum Ratings
- 8 ESD Ratings
- 9 Recommended Operating Conditions
- 10Thermal Information
- 11Electrical Characteristics
- 12SPI Timing Requirements
-
13Detailed Description
- 13.1 Overview
- 13.2 Functional Block Diagram
- 13.3
Feature Description
- 13.3.1 Three Phase Smart Gate Drivers
- 13.3.2 DVDD Linear Voltage Regulator
- 13.3.3 Pin Diagrams
- 13.3.4 Low-Side Current-Shunt Amplifiers
- 13.3.5
Gate Driver Protective Circuits
- 13.3.5.1 VM Supply and VDRAIN Undervoltage Lockout (UVLO)
- 13.3.5.2 VCP Charge-Pump and VGLS Regulator Undervoltage Lockout (GDUV)
- 13.3.5.3 MOSFET VDS Overcurrent Protection (VDS_OCP)
- 13.3.5.4 VSENSE Overcurrent Protection (SEN_OCP)
- 13.3.5.5 Gate Driver Fault (GDF)
- 13.3.5.6 Overcurrent Soft Shutdown (OCP Soft)
- 13.3.5.7 Thermal Warning (OTW)
- 13.3.5.8 Thermal Shutdown (OTSD)
- 13.3.5.9 Fault Response Table
- 13.4 Device Functional Modes
- 13.5 Programming
- 13.6
Register Maps
- 13.6.1 Status Registers
- 13.6.2
Control Registers
- 13.6.2.1 Driver Control Register (address = 0x02h)
- 13.6.2.2 Gate Drive HS Register (address = 0x03h)
- 13.6.2.3 Gate Drive LS Register (address = 0x04h)
- 13.6.2.4 OCP Control Register (address = 0x05h)
- 13.6.2.5 CSA Control Register (address = 0x06h)
- 13.6.2.6 Driver Configuration Register (address = 0x07h)
-
14Application and Implementation
- 14.1 Application Information
- 14.2
Typical Application
- 14.2.1
Primary Application
- 14.2.1.1 Design Requirements
- 14.2.1.2 Detailed Design Procedure
- 14.2.1.3 Application Curves
- 14.2.1
Primary Application
- 15Power Supply Recommendations
- 16Layout
- 17Device and Documentation Support
- 18Mechanical, Packaging, and Orderable Information
13.3.1.2.2 Hardware Interface
Hardware interface devices convert the four SPI pins into four resistor configurable inputs, GAIN, IDRIVE, MODE, and VDS. This allows for the application designer to configure the most commonly used device settings by tying the pin logic high or logic low, or with a simple pullup or pulldown resistor. This removes the requirement for an SPI bus from the external controller. General fault information can still be obtained through the nFAULT pin.
- The GAIN pin configures the current shunt amplifier gain.
- The IDRIVE pin configures the gate drive current strength.
- The MODE pin configures the PWM control mode.
- The VDS pin configures the voltage threshold of the VDS overcurrent monitors.
For more information on the hardware interface, see the Section 13.3.3 section.
Figure 13-8 SPI
Figure 13-9 Hardware Interface