ZHCSR67 July 2020 DRV8353M
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Absolute Maximum Ratings
- 8 ESD Ratings
- 9 Recommended Operating Conditions
- 10Thermal Information
- 11Electrical Characteristics
- 12SPI Timing Requirements
-
13Detailed Description
- 13.1 Overview
- 13.2 Functional Block Diagram
- 13.3
Feature Description
- 13.3.1 Three Phase Smart Gate Drivers
- 13.3.2 DVDD Linear Voltage Regulator
- 13.3.3 Pin Diagrams
- 13.3.4 Low-Side Current-Shunt Amplifiers
- 13.3.5
Gate Driver Protective Circuits
- 13.3.5.1 VM Supply and VDRAIN Undervoltage Lockout (UVLO)
- 13.3.5.2 VCP Charge-Pump and VGLS Regulator Undervoltage Lockout (GDUV)
- 13.3.5.3 MOSFET VDS Overcurrent Protection (VDS_OCP)
- 13.3.5.4 VSENSE Overcurrent Protection (SEN_OCP)
- 13.3.5.5 Gate Driver Fault (GDF)
- 13.3.5.6 Overcurrent Soft Shutdown (OCP Soft)
- 13.3.5.7 Thermal Warning (OTW)
- 13.3.5.8 Thermal Shutdown (OTSD)
- 13.3.5.9 Fault Response Table
- 13.4 Device Functional Modes
- 13.5 Programming
- 13.6
Register Maps
- 13.6.1 Status Registers
- 13.6.2
Control Registers
- 13.6.2.1 Driver Control Register (address = 0x02h)
- 13.6.2.2 Gate Drive HS Register (address = 0x03h)
- 13.6.2.3 Gate Drive LS Register (address = 0x04h)
- 13.6.2.4 OCP Control Register (address = 0x05h)
- 13.6.2.5 CSA Control Register (address = 0x06h)
- 13.6.2.6 Driver Configuration Register (address = 0x07h)
-
14Application and Implementation
- 14.1 Application Information
- 14.2
Typical Application
- 14.2.1
Primary Application
- 14.2.1.1 Design Requirements
- 14.2.1.2 Detailed Design Procedure
- 14.2.1.3 Application Curves
- 14.2.1
Primary Application
- 15Power Supply Recommendations
- 16Layout
- 17Device and Documentation Support
- 18Mechanical, Packaging, and Orderable Information
13.3.1.4.4 MOSFET VDS Monitors
The gate drivers implement adjustable VDS voltage monitors to detect overcurrent or short-circuit conditions on the external power MOSFETs. When the monitored voltage is greater than the VDS trip point (VVDS_OCP) for longer than the deglitch time (tOCP), an overcurrent condition is detected and action is taken according to the device VDS fault mode.
The high-side VDS monitors measure the voltage between the VDRAIN and SHx pins. The low-side VDS monitors measure the voltage between the SHx and SPx pins. If the current shunt amplifier is unused, tie the SP pins to the common ground point of the external half-bridges.
For the SPI devices, the low-side VDS monitor reference point can be changed between the SPx and SNx pins if desired with the LS_REF register setting. This is only for the low-side VDS monitor. The high-side VDS monitor stays between the VDRAIN and SHx pins.
The VVDS_OCP threshold is programmable between 0.06 V and 2 V on SPI device and between 0.06 V and 1 V on hardware interface devices. Additional information on the VDS monitor levels are described in the Section 13.6 section for SPI devices and in the Section 13.3.3 section hardware interface device.
Figure 13-15 DRV8353M VDS Monitors