PD_15-12

PD_11-8

PD_7-4

PD_3-0

Active in all device control modes. The pin has internal 1-MΩ weak pulldown resistor. The pin triggers PCIe RX detect state machine when toggled.

• High: power down
• Low: power up normal operation.

Each PD pin sets control for a bank of 8 lanes (4 from Side A and 4 from Side B) to provide flexibility for x4 and x8 bifurcation:

• PD_15-12: Lanes 15-12, both Side A and B
• PD_11-8: Lanes 11-8, both Side A and B
• PD_7-4: Lanes 7-4, both Side A and B
• PD_3-0: Lanes 3-0, both Side A and B

PCIe hot plug insertion implementation varies from system to system. One way to implement will be to use CEM interface PRSNT# signal. For PCIe x16 application all four PD signals can be shorted together and connect to CEM interface PRSNT# signal.

A_ADDR1_15-8

A_ADDR0_15-8

A_ADDR1_7-0

A_ADDR0_7-0

B_ADDR1_15-8

B_ADDR0_15-8

B_ADDR1_7-0

B_ADDR0_7-0

5-level input pins as implemented by pull-down resistor on the pin according to Table 7-5.

These pins are sampled at device power-up only. Sets SMBus / I2C secondary address according to Table 7-3. Each set of ADDR1 and ADDR0 pins defines the addresses for bank of 8 lanes:

• A_ADDR1_15-8, A_ADDR0_15-8: Lanes 15-8 of Side A
• A_ADDR1_7-0, A_ADDR0_7-0: Lanes 7-0 of Side A
• B_ADDR1_15-8, B_ADDR0_15-8: Lanes 15-8 of Side B
• B_ADDR1_7-0, B_ADDR0_7-0: Lanes 7-0 of Side B

#FIG_G1Z_YVZ_CPB shows how I2C secondary addresses are accessed for specific lanes.