In PCIe Gen 3.0 and 4.0 applications, the specification requires Rx-Tx (of root-complex and endpoint) link training to establish and optimize signal conditioning settings. In link training, the Rx partner requests a series of FIR – preshoot and deemphasis coefficients (10 Presets) from the Tx partner. The Rx partner includes 7-levels of CTLE followed by a single tap DFE. The link training would pre-condition the signal, with an equalized link between the root-complex and endpoint resulting an optimized link. Note that there is no link training in PCIe Gen 1.0 (2.5 Gbps) or PCIe Gen 2.0 (5.0 Gbps) applications.

The DS160PR1601 is designed with linear datapth to pass the Tx Preset signaling (by root complex and end point) onto the Rx (of root complex and end point) for a PCIe link to train and optimize for the Rx equalization settings. The linear redriver helps extend the PCB trace reach distance by boosting the attenuated signals with its own equalization, which allows the Rx to recover signals more easily. The device must be placed in between the Tx and Rx (of root complex and end point) such a way that signal swing of both upstream and downstream signals stays within the linearity range of the device. Adjustments to the DS160PR1601 EQ setting should be performed based on the channel loss to optimize the eye opening in the Rx partner. The available EQ gain settings are provided in Table 7-4. For most PCIe systems the default Flat gain setting of 0 dB (flat_gain = 101) would be sufficient.

The DS160PR1601 can be optimized for a given system utlizing its two configuration modes – SMBus/I²C Primary mode and SMBus/I²C Secondary mode. In SMBus/I²C modes the SCL, SDA pins must be pulled up to a 3.3 V supply with a pull-up resistor. The value of the resistor depends on total bus capacitance. 4.7 kΩ is a good first approximation for a bus capacitance of 10 pF.

#T5877368-6 shows a simplified schematic for x16 lane configuration in SMBus/I²C Primary mode.