The design procedure for active cable applications is as follows:

1. Determine the maximum current draw required for one or more of the DS250DF230 retimers on the paddle card. This may impact the selection of the regulator for the 2.5-V supply rail. To calculate the maximum current draw, multiply the maximum transient power supply current by the total number of DS250DF230 devices.
2. Determine the maximum operational power consumption for the purpose of thermal analysis. There are two ways to approach this calculation:
   1. Maximum mission-mode operational power consumption is when all channels are locked and re-transmitting the data which is received. PRBS pattern checkers/generators are not used in this mode because normal traffic cannot be checked with a PRBS checker. For this calculation, multiply the worst-case power consumption in mission mode by the total number of DS250DF230 devices.
   2. Maximum debug-mode operational power consumption is when all channels are locked and re-transmitting the data which is received. At the same time, some channels’ PRBS checkers or generators may be enabled. For this calculation, multiply the worst-case power consumption in debug mode by the total number of DS250DF230 devices.
3. Determine the SMBus address for one or more of the DS250DF230 retimers. The ADDR[1:0] pins can be left floating for an 8-bit SMBus slave address of 0x44. For the second DS250DF230, a single pullup or pulldown resistor can be used on one address pin. For example, with ADDR0 = Float and ADDR1 = 1 kΩ to GND，the 8-bit SMBus slave address will be 0x34.
4. Determine if the device will be configured from EEPROM (SMBus Master Mode) or from the system I2C bus (SMBus Slave Mode).
   1. If SMBus Master Mode will be used, provisions must be made for an EEPROM on the board with 8-bit SMBus address 0xA0. Refer to SMBus Master Mode for more details on SMBus Master Mode including EEPROM size requirements.
   2. If SMBus Slave Mode will be used for all device configurations, for example when one or more of the retimers is configured with a microcontroller, an EEPROM is not needed.
5. Make provisions in the schematic and layout for standard decoupling capacitors between the device VDD supply and GND. Refer to the pin function description in Pin Configuration and Functions for more details.
6. Make provisions in the schematic and layout for a 30.72-MHz (±100 ppm) or 25-MHz (±100 ppm) single-ended CMOS clock. The DS250DF230 retimer buffers the clock on the CAL_CLK_IN pin and presents the buffered clock on the CAL_CLK_OUT pin. When using two Retimers on a paddle card, only one 30.72-MHz or 25-MHz clock is required. The CAL_CLK_OUT pin of one retimer can be connected to the CAL_CLK_IN pin of the other retimer.
7. Connect the INT_N open-drain output to the paddle card MCU if interrupt monitoring is desired, otherwise leave it floating. Note that multiple retimers’ INT_N outputs can be connected together because this is an open-drain output. The common INT_N net should be pulled high.
8. If the application requires initial CDR lock acquisition at the ambient temperature extremes defined in Recommended Operating Conditions, take care to ensure the operating junction temperature is met as well as the CDR stay-in-lock junction temperature range defined in Electrical Characteristics. For example, if initial CDR lock acquisition occurs at an junction temperature of 110°C, then maintaining CDR lock would require the junction temperature on DS250DF230 to be kept above (110°C – TEMP_LOCK–).