5 Pin Configuration and Functions

Figure 5-1 RNQ Package,40-Pin WQFN(Top View)

Table 5-1 Pin Functions

PIN		TYPE⁽¹⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾	DESCRIPTION
DONEn	7	O, 3.3 V open drain	In SMBus/I²C Primary mode: Indicates the completion of a valid EEPROM register load operation. External pullup resistor such as 4.7 kΩ required for operation. High: External EEPROM load failed or incomplete Low: External EEPROM load successful and complete In SMBus/I²C Secondary/Pin mode: This output is High-Z. The pin can be left floating.
MODE	25	I, 5-level	Sets device control configuration modes. 5-level IO pin as provided in Table 7-4. The pin can be exercised at device power up or in normal operation mode. L0: Pin mode – strap pins solely sets device control configuration settings. L1: SMBus/I²C Primary mode – device control configuration is read from external EEPROM. When the DS320PR410 has finished reading from the EEPROM successfully, it will drive the DONEn pin LOW. SMBus/I²C secondary operation is available in this mode before, during or after EEPROM reading. Note: during EEPROM reading if the external SMBus/I²C primary wants to access DS320PR410 registers it must support arbitration. L2: SMBus/I²C Secondary mode – an external controller with SMBus/I²C primary sets device control configuration settings. L3 and L4 (Float): RESERVED – TI internal test modes.
EQ0 / ADDR0	23	I, 5-level	In Pin mode: Sets receiver linear equalization (CTLE) boost for channels 0-3 as provided in Table 7-1. These pins are sampled at device power-up only. In SMBus/I²C mode: Sets SMBus / I²C secondary address as provided in Table 7-5. These pins are sampled at device power-up only. In this mode, equalization boost is configured by setting SMBus / I²C register bits.
EQ1 / ADDR1	24	I, 5-level
GAIN / SDA	27	I, 5-level / I/O, 3.3 V LVCMOS, open drain	In Pin mode: Flat gain (DC and AC) from the input to the output of the device for channels 0-3. The pin is sampled at device power-up only. In SMBus/I²C mode: 3.3 V SMBus/I²C data. External 1 kΩ to 5 kΩ pullup resistor is required as per SMBus / I²C interface standard. In this mode, Flat gain is configured by setting SMBus / I²C register bits.
GND	1, 8, 11, 18, 21, 28, 31, 38, EP	P	Ground reference for the device. EP: the Exposed Pad at the bottom of the QFN package. It is used as the GND return for the device. The EP should be connected to one or more ground planes through the low resistance path. A via array provides a low impedance path to GND. The EP also improves thermal dissipation.
PD	6	I, 3.3 V LVCMOS	2-level logic controlling the operating state of the redriver. Active in all device control modes. The pin has internal 1-MΩ weak pull-down resistor. The pin triggers PCIe Rx detect state machine when toggled. High: power down for channels 0-3 Low: power up, normal operation for channels 0-3
READ_EN_N	22	I, 3.3 V LVCMOS	In SMBus/I²C Primary mode: After device power up, when the pin is low, the pin initiates the SMBus / I²C Primary mode EEPROM read function. When EEPROM read is complete (indicated by assertion of DONEn low), this pin can be held low for normal device operation. During the EEPROM load process the device’s signal path is disabled. In SMBus/I²C Secondary and Pin modes: In these modes the pin is not used. The pin can be left floating. The pin has internal 1-MΩ weak pull-down resistor.
RSVD	2	—	Reserved use for TI. The pin must be left floating (NC).
RX_DET / SCL	26	I, 5-level / I/O, 3.3 V LVCMOS, open drain	In Pin mode: Sets receiver detect state machine options as provided in Table 7-3. The pin is sampled at device power-up only. In SMBus/I²C mode: 3.3V SMBus/I²C clock. External 1 kΩ to 5 kΩ pullup resistor is required as per SMBus / I²C interface standard. In this mode, receiver detect state machine is configured by setting SMBus / I²C register bits.
RX0N	30	I	Inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 0.
RX0P	29	I	Non-inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 0.
RX1N	33	I	Inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 1.
RX1P	32	I	Non-inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 1.
RX2N	37	I	Inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 2.
RX2P	36	I	Non-inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 2.
RX3N	40	I	Inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 3.
RX3P	39	I	Non-inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 3.
TX0N	19	O	Inverting pin for 100 Ω differential driver output. Channel 0.
TX0P	20	O	Non-inverting pin for 100 Ω differential driver output. Channel 0.
TX1N	16	O	Inverting pin for 100 Ω differential driver output. Channel 1.
TX1P	17	O	Non-inverting pin for 100 Ω differential driver output. Channel 1.
TX2N	12	O	Inverting pin for 100 Ω differential driver output. Channel 2.
TX2P	13	O	Non-inverting pin for 100 Ω differential driver output. Channel 2.
TX3N	9	O	Inverting pin for 100 Ω differential driver output. Channel 3.
TX3P	10	O	Non-inverting pin for 100 Ω differential driver output. Channel 3.
VCC	14, 15, 34, 35	P	Power supply pins. VCC = 3.3 V ±10%. The VCC pins on this device should be connected through a low-resistance path to the board VCC plane. Install a decoupling capacitor to GND near each VCC pin.

(1) I = input, O = output, P = power