SNLS043H May   2000  – January 2016 DS90CR216A , DS90CR286A , DS90CR286A-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics: Receiver
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 LVDS Receivers
        1. 7.3.1.1 LVDS Input Termination
      2. 7.3.2 Phase Locked Loop (PLL)
      3. 7.3.3 Serial LVDS-to-Parallel LVCMOS Converter
      4. 7.3.4 LVCMOS Drivers
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Cables
        2. 8.2.2.2 Bit Resolution and Operating Frequency Compatibility
        3. 8.2.2.3 Data Mapping between Receiver and Endpoint Panel Display
        4. 8.2.2.4 RSKM Interoperability
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

4 Revision History

Changes from G Revision (August 2015) to H Revision

  • Changed Figure 6 and Figure 7 to clarify that TxIN on Tx is the same as RxOUT on Rx Go
  • Changed "limit output amplitude" to "reduce reflections from long board traces" for clarificationGo
  • Deleted 0.01-µF and 0.001-µF caps from required DC power supply coupling capacitorsGo
  • Deleted "Setup and Hold Time" label from the Rx strobe window diagram to clarify RSKM conceptGo
  • Changed direction of Rx strobe position shift for correct left and right RSKM margin shift behaviorGo
  • Added new Application Note reference for RSKM improvementGo
  • Added improved layout guidelinesGo
  • Changed Figure 28 graphic to clarify the use of series resistors on LVCMOS output Go

Changes from F Revision (February 2013) to G Revision

  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo
  • Changed specification title to clarify 3.3 V LVCMOS and not standard 5 V CMOSGo
  • Changed title and graphic of figure to clarify 3.3 V LVCMOS and not standard 5 V CMOSGo
  • Changed title of DS90CR286A mapping to clarify the make-up of the LVDS linesGo
  • Changed title of DS90CR216A mapping to clarify the make-up of the LVDS linesGo
  • Added cycle-to-cycle jitter value of 250 ps instead of TBD psGo

Changes from E Revision (February 2013) to F Revision

  • Changed layout of National Data Sheet to TI formatGo
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