ZHCSMR3A november   2020  – november 2020 DS90UB633A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1.     Pin Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Recommended Serializer Timing For PCLK
    7. 6.7  AC Timing Specifications (SCL, SDA) - I2C-Compatible
    8. 6.8  Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-Compatible
    9. 6.9  Serializer Switching Characteristics
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Frame Format
      2. 7.3.2 Line Rate Calculations for the DS90UB633A/662
      3. 7.3.3 Error Detection
      4. 7.3.4 Synchronizing Multiple Cameras
      5. 7.3.5 General Purpose I/O (GPIO) Descriptions
      6. 7.3.6 LVCMOS V(VDDIO) Option
      7. 7.3.7 Pixel Clock Edge Select (TRFB / RRFB)
      8. 7.3.8 Power Down
    4. 7.4 Device Functional Modes
      1. 7.4.1 DS90UB633A/662 Operation With External Oscillator as Reference Clock
      2. 7.4.2 DS90UB633A/662 Operation With Pixel Clock From Imager as Reference Clock
      3. 7.4.3 MODE Pin on Serializer
      4. 7.4.4 Internal Oscillator
      5. 7.4.5 Built-In Self Test
      6. 7.4.6 BIST Configuration and Status
      7. 7.4.7 Sample BIST Sequence
    5. 7.5 Programming
      1. 7.5.1 Programmable Controller
      2. 7.5.2 Description of Bidirectional Control Bus and I2C Modes
      3. 7.5.3 I2C Pass-Through
      4. 7.5.4 Slave Clock Stretching
      5. 7.5.5 IDX Address Decoder on the Serializer
      6. 7.5.6 Multiple Device Addressing
    6. 7.6 Register Maps
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Over Coax
      2. 8.1.2 Power-Up Requirements and PDB Pin
      3. 8.1.3 AC Coupling
      4. 8.1.4 Transmission Media
    2. 8.2 Typical Applications
      1. 8.2.1 Coax Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 STP Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Interconnect Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information
    2. 12.2 Tape and Reel Information

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机械数据 (封装 | 引脚)
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7.4.1 DS90UB633A/662 Operation With External Oscillator as Reference Clock

In some applications, the pixel clock that comes from the imager can have jitter which exceeds the tolerance of the DS90UB633A/662 chipsets. In this case, operate the DS90UB633A-Q1 device by using an external clock source as the reference clock for the DS90UB633A/662 chipsets. This is the recommended operating mode. The external oscillator clock output goes through a divide-by-2 circuit in the DS90UB633A-Q1 serializer, and this divided clock output is used as the reference clock for the imager. The output data and pixel clock from the imager are then fed into the DS90UB633A-Q1 device. Figure 7-4 shows the operation of the DS90UB633A/662 chipsets while using an external automotive grade oscillator.

GUID-74ABA51D-B720-4308-9E93-7E6C475E3872-low.gifFigure 7-4 DS90UB633A-Q1/662-Q1 Operation in the External Oscillator Mode

When the DS90UB633A-Q1 device is operated using an external oscillator, the GPO3 pin on the DS90UB633A-Q1 is the input pin for the external oscillator. In applications where the DS90UB633A-Q1 device is operated from an external oscillator, the divide-by-2 circuit in the DS90UB633A-Q1 device feeds back the divided clock output to the imager device through GPO2 pin. The pixel clock to external oscillator ratios must be fixed for the 12–bit mode and the 10–bit mode. In the 10-bit mode, the pixel clock frequency divided by the external oscillator frequency must be 2. In the 12-bit mode, the pixel clock frequency divided by the external oscillator frequency must be 1.5. For example, if the external oscillator frequency is 48 MHz in the 10-bit mode, the pixel clock frequency of the imager must be twice of the external oscillator frequency, that is, 96 MHz. If the external oscillator frequency is 48 MHz in the 12-bit mode, the pixel clock frequency of the imager must be 1.5 times of the external oscillator frequency, that is, 72 MHz. For the range of PCLK frequency and the external clock input frequency to GPO3 in 10-bit and 12-bit modes, see Section 6.3.

When PCLK signal edge is detected, and 0x03[1] = 0, the DS90UB633A-Q1 switches from internal oscillator mode to an external PCLK. Upon removal of PCLK input, the device switches back into internal oscillator mode. In external oscillator mode, GPO2 and GPO3 on the serializer cannot act as the output of the input signal coming from GPIO2 or GPIO3 on the deserializer.

Table 7-1 Device Functional Mode With Example XCLKIN = 48 MHz
MODEGPIO3 XCLKINGPIO2 XCLKOUT = XCLKIN / 2RATIOINPUT PCLK FREQUENCY = XLCKIN * RATIO
10-bit48 MHz24 MHz296 MHz
12-bit48 MHz24 MHz1.572 MHz
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