The proxy master timing parameters are based on the REFCLK timing. Timing accuracy for the I2C proxy master based on the REFCLK clock source attached to the DS90UB662-Q1 deserializer. Before REFCLK is applied the deserializer will default to internal reference clock with accuracy of 25 MHz ±10%. The I2C Master regenerates the I2C read or write access using timing controls in the registers 0x0A and 0x0B (Table 7-28 and Table 7-29) to regenerate the clock and data signals to meet the desired I2C timing in standard, fast, or fast-plus modes of operation.

I2C Master SCL High Time is set in register 0x0A[7:0]. This field configures the high pulse width of the SCL output when the Serializer is the Master on the local deserializer I2C bus. The default value is set to provide a minimum 5-µs SCL high time with the reference clock at 25 MHz + 100 ppm including four additional oscillator clock periods or synchronization and response time. Units are 40 ns for the nominal oscillator clock frequency, giving Min_delay = 40 ns × (SCL_HIGH_TIME + 4).

I2C Master SCL Low Time is set in register 0x0B[7:0]. This field configures the low pulse width of the SCL output when the Serializer is the Master on the local deserializer I2C bus. This value is also used as the SDA setup time by the I2C Slave for providing data prior to releasing SCL during accesses over the Bidirectional Control Channel. The default value is set to provide a minimum 5-µs SCL high time with the reference clock at 25 MHz + 100ppm including four additional oscillator clock periods or synchronization and response time. Units are 40 ns for the nominal oscillator clock frequency, giving Min_delay = 40 ns × (SCL_HIGH_TIME + 4). See Table 7-16 example settings for Standard mode, Fast mode and Fast-mode Plus timing.