Figure 8-4 Typical Connection Diagram Coaxial
With Internal 1.1-V LDO
Note: - The decoupling capacitors for
VDD11 are different between the two typical application diagrams because VDD_SEL is pulled
to different levels. See the Pin Functions table for
more information. - FB2, F3 may be required depending on
system power supply noise levels - FB1-FB4: DCR ≤ 25mΩ; Z =
120Ω@100MHz - C1, C2, C3, C4 (see Design Parameters Values
Table) - R1, R2 (see IDX Resistor Values
Table) - R3, R4 (see MODE Resistor Values
Table) - RTERM = 50Ω
Figure 8-5 Typical Connection Diagram STP With
External 1.1-V supply
Note: - The decoupling capacitors for
VDD11 are different between the two typical application diagrams because VDD_SEL is pulled
to different levels. See the Pin Functions table for
more information. - FB1-FB7: DCR ≤ 25mΩ; Z = 120Ω@100MHz - C1, C2, C3, C4 (see Design Parameters Values
Table) - R1, R2 (see IDX Resistor Values
Table) - R3, R4 (see MODE Resistor Values
Table) - RTERM = 50Ω