The FPC202 has two master I2C interfaces for managing up to two ports, referred to as "downstream" ports. Each downstream I2C interface can be configured to operate with an SCL clock frequency between 100 kHz and 400 kHz. The downstream I2C master supports clock stretching.

The SFF-8472 and SFF-8431 specifications define up to two logical device addresses per SFP port: 0xA0 and 0xA2. The SFF-8436 specification defines one logical device address per QSFP port: 0xA0. By default, both 0xA0 and 0xA2 are directly addressable by the upstream host controller. The directly accessible addresses may be modified through I2C writes to the FPC202 such that any valid I2C address is directly accessible. Refer to Table 7-6 (I2C) and Table 7-7 (SPI). The FPC202 uses this address mapping scheme to decode the port and device address and perform a downstream I2C read or write operation. This is known as a remote access. Remote accesses have the highest priority when accessing the downstream module. If there is an on-going periodic pre-fetch or scheduled write, these operations will be stopped at the next byte boundary and the remote access will be executed. The periodic pre-fetch or schedule write operation will be resumed after the remote access finishes. Note that the periodic pre-fetch will begin from the starting register offset of the pre-fetch range rather than where it left off during the interruption. If a remote access is attempted during an interrupt-driven pre-fetch, the interrupt-driven pre-fetch will finish and the remote access will be executed afterwards. If an autonomous access (pre-fetch or scheduled write) occurs during a remote access, the autonomous access will be executed after the remote access is completed.

All the bits of the downstream device address can be modified for direct read/write access, allowing communication with addresses 0x10, 0x20, ..., 0xE0, and 0xF0. Modified addresses cannot be used with other features such as pre-fetching and scheduled write. In SPI mode, accessing a register in the pre-fetched range from a modified address will return the pre-fetched value from the 0xA0 or 0xA2 address. To avoid this, the gate bit must be reset before attempting such an access.