Accessing a specific register on the INA226-Q1 is accomplished by writing the appropriate value to the register pointer. Refer to Table 7-1 for a complete list of registers and corresponding addresses. The value for the register pointer (as shown in Figure 6-7) is the first byte transferred after the slave address byte with the R/ W bit low. Every write operation to the device requires a value for the register pointer.

Writing to a register begins with the first byte transmitted by the master. This byte is the slave address, with the R/ W bit low. The device then acknowledges receipt of a valid address. The next byte transmitted by the master is the address of the register which data is written to. This register address value updates the register pointer to the desired register. The next two bytes are written to the register addressed by the register pointer. The device acknowledges receipt of each data byte. The master can terminate data transfer by generating a start or stop condition.

When reading from the device, the last value stored in the register pointer by a write operation determines which register is read during a read operation. To change the register pointer for a read operation, a new value must be written to the register pointer. This write is accomplished by issuing a slave address byte with the R/ W bit low, followed by the register pointer byte. No additional data are required. The master then generates a start condition and sends the slave address byte with the R/ W bit high to initiate the read command. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the register pointer. This byte is followed by an Acknowledge from the master; then the slave transmits the least significant byte. The master acknowledges receipt of the data byte. The master can terminate data transfer by generating a Not-Acknowledge after receiving any data byte, or generating a start or stop condition. If repeated reads from the same register are desired, continually sending the register pointer bytes is not necessary; the device retains the register pointer value until the value is changed by the next write operation.

Figure 6-4 shows the write operation timing diagram. Figure 6-5 shows the read operation timing diagram.

1. The value of the Slave Address byte is determined by the settings of the A0 and A1 pins. Refer to Table 6-2.

Figure 6-4 Timing Diagram for Write Word Format

1. The value of the Slave Address byte is determined by the settings of the A0 and A1 pins. Refer to Table 6-2.
2. Read data is from the last register pointer location. If a new register is desired, the register pointer must be updated. See Figure 6-7.
3. ACK by Master can also be sent.

Figure 6-5 Timing Diagram for Read Word Format

Figure 6-6 shows the timing diagram for the SMBus Alert response operation. Figure 6-7 illustrates a typical register pointer configuration.

1. The value of the Slave Address Byte is determined by the settings of the A0 and A1 pins. Refer to Table 6-2.

Figure 6-6 Timing Diagram for SMBus ALERT

1. The value of the Slave Address Byte is determined by the settings of the A0 and A1 pins. Refer to Table 6-2.

Figure 6-7 Typical Register Pointer Set