ZHCSL81A May   2020  – June 2021 INA229-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements (SPI)
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Versatile High Voltage Measurement Capability
      2. 7.3.2 Internal Measurement and Calculation Engine
      3. 7.3.3 Low Bias Current
      4. 7.3.4 High-Precision Delta-Sigma ADC
        1. 7.3.4.1 Low Latency Digital Filter
        2. 7.3.4.2 Flexible Conversion Times and Averaging
      5. 7.3.5 Shunt Resistor Drift Compensation
      6. 7.3.6 Integrated Precision Oscillator
      7. 7.3.7 Multi-Alert Monitoring and Fault Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. 7.5.1.1 SPI Frame
    6. 7.6 Register Maps
      1. 7.6.1 INA229-Q1 Registers
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Measurement Range and Resolution
      2. 8.1.2 Current , Power, Energy, and Charge Calculations
      3. 8.1.3 ADC Output Data Rate and Noise Performance
      4. 8.1.4 Input Filtering Considerations
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select the Shunt Resistor
        2. 8.2.2.2 Configure the Device
        3. 8.2.2.3 Program the Shunt Calibration Register
        4. 8.2.2.4 Set Desired Fault Thresholds
        5. 8.2.2.5 Calculate Returned Values
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 接收文档更新通知
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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High-Precision Delta-Sigma ADC

The integrated ADC is a high-performance, low-offset, low-drift, delta-sigma ADC designed to support bidirectional current flow at the shunt voltage measurement channel. The measured inputs are selected through the high-voltage input multiplexer to the ADC inputs as shown in Figure 7-1. The ADC architecture enables lower drift measurement across temperature and consistent offset measurements across the common-mode voltage, temperature, and power supply variations. A low-offset ADC is preferred in current sensing applications to provide a near 0-V offset voltage that maximizes the useful dynamic range of the system.

The INA229-Q1 can measure the shunt voltage, bus voltage, and die temperature, or a combination of any based on the selected MODE bits setting in the ADC_CONFIG register. This permits selecting modes to convert only the shunt voltage or bus voltage to further allow the user to configure the monitoring function to fit the specific application requirements. When no averaging is selected, once an ADC conversion is completed, the converted values are independently updated in their corresponding registers where they can be read through the digital interface at the time of conversion end. The conversion time for shunt voltage, bus voltage, and temperature inputs are set independently from 50 µs to 4.12ms depending on the values programmed in the ADC_CONFIG register. Enabled measurement inputs are converted sequentially so the total time to convert all inputs depends on the conversion time for each input and the number of inputs enabled. When averaging is used, the intermediate values are subsequently stored in an averaging accumulator, and the conversion sequence repeats until the number of averages is reached. After all of the averaging has been completed, the final values are updated in the corresponding registers that can then be read. These values remain in the data output registers until they are replaced by the next fully completed conversion results. In this case, reading the data output registers does not affect a conversion in progress.

The ADC has two conversion modes—continuous and triggered—set by the MODE bits in ADC_CONFIG register. In continuous-conversion mode, the ADC will continuously convert the input measurements and update the output registers as described above in an indefinite loop. In triggered-conversion mode, the ADC will convert the input measurements as described above, after which the ADC will go into shutdown mode until another single-shot trigger is generated by writing to the MODE bits. Writing the MODE bits will interrupt and restart triggered or continuous conversions that are in progress. Although the device can be read at any time, and the data from the last conversion remains available, the Conversion Ready flag (CNVRF bit in DIAG_ALRT register) is provided to help coordinate triggered conversions. This bit is set after all conversions and averaging is completed.

The Conversion Ready flag (CNVRF) clears under these conditions:

  • Writing to the ADC_CONFIG register (except for selecting shutdown mode); or
  • Reading the DIAG_ALRT Register

While the INA229-Q1 device is used in either one of the conversion modes, a dedicated digital engine is calculating the current, power, charge and energy values in the background as described in Section 7.3.2. In triggered mode, the accumulation registers (ENERGY and CHARGE) are invalid, as the device does not keep track of elapsed time. For applications that need critical measurements in regards to accumulation of time for energy and charge measurements, the device must be configured to use continuous conversion mode, as the accumulated results are continuously updated and can provide true system representation of charge and energy consumption in a system. All of the calculations are performed in the background and do not contribute to conversion time.

For applications that must synchronize with other components in the system, the INA229-Q1 conversion can be delayed by programming the CONVDLY bits in CONFIG register in the range between 0 (no delay) and 510 ms. The resolution in programming the conversion delay is 2 ms. The conversion delay is set to 0 by default. Conversion delay can assist in measurement synchronization when multiple external devices are used for voltage or current monitoring purposes. In applications where an time aligned voltage and current measurements are needed, two devices can be used with the current measurement delayed such that the external voltage and current measurements will occur at approximately the same time. Keep in mind that even though the internal time base for the ADC is precise, synchronization will be lost over time due to internal and external time base mismatch.