米6体育平台手机版

ZHCSJM1A April 2019 – June 2019 INA818

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

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7.5 Electrical Characteristics

at T_A = 25°C, V_S = ±15 V, R_L = 10 kΩ, V_REF = 0 V, and G = 1 (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT
V_OSI	Input stage offset voltage⁽¹⁾⁽³⁾			10	35	µV
		T_A = –40°C to 125°C⁽²⁾			75	µV
		drift vs temperature, T_A = –40°C to 125°C			0.4	µV/°C
V_OSO	Output stage offset voltage⁽¹⁾⁽³⁾			50	300	µV
		T_A = –40°C to 125°C⁽²⁾			800	µV
		drift vs temperature, T_A = –40°C to 125°C			5	µV/°C
PSRR	Power-supply rejection ratio	G = 1, RTI	110	120		dB
		G = 10, RTI	114	130
		G = 100, RTI	130	135
		G = 1000, RTI	136	140
z_id	Differential impedance			100 \|\| 1		GΩ \|\| pF
z_ic	Common-mode impedance			100 \|\| 4		GΩ \|\| pF
	RFI filter, –3-dB frequency			32		MHz
V_CM	Operating input range⁽⁴⁾		(V–) + 2		(V+) – 2	V
V_CM	Operating input range⁽⁴⁾	V_S = ±2.25 V to ±18 V, T_A = –40°C to 125°C	See Figure 51 to Figure 54			V
	Input overvoltage range	T_A = –40°C to 125°C⁽²⁾			±60	V
CMRR	Common-mode rejection ratio	At DC to 60 Hz, RTI, V_CM = (V–) + 2 V to (V+) – 2 V, G = 1	90	105		dB
		At DC to 60 Hz, RTI, V_CM = (V–) + 2 V to (V+) – 2 V, G = 10	110	125
		At DC to 60 Hz, RTI, V_CM = (V–) + 2 V to (V+) – 2 V, G = 100	130	145
		At DC to 60 Hz, RTI, V_CM = (V–) + 2 V to (V+) – 2 V, G = 1000	140	150
BIAS CURRENT
I_B	Input bias current	V_CM = V_S / 2		0.15	0.5	nA
I_B	Input bias current	T_A = –40°C to 125°C			2	nA
I_OS	Input offset current	V_CM = V_S / 2		0.15	0.5	nA
I_OS	Input offset current	T_A = –40°C to 125°C			2	nA
NOISE VOLTAGE
e_NI	Input stage voltage noise⁽⁶⁾	f = 1 kHz, G = 100, R_S = 0 Ω		8		nV/√Hz
e_NI	Input stage voltage noise⁽⁶⁾	f_B = 0.1 Hz to 10 Hz, G = 100, R_S = 0 Ω		0.19		µV_PP
e_NO	Output stage voltage noise⁽⁶⁾	f = 1 kHz, R_S = 0 Ω		80		nV/√Hz
e_NO	Output stage voltage noise⁽⁶⁾	f_B = 0.1 Hz to 10 Hz, R_S = 0 Ω		2.6		µV_PP
I_n	Noise current	f = 1 kHz		130		fA/√Hz
I_n	Noise current	f_B = 0.1 Hz to 10 Hz, G = 100		4.7		pA_PP
GAIN
	Gain equation			1 + (50 kΩ / R_G)		V/V
G	Gain		1		1000	V/V
GE	Gain error	G = 1, V_O = ±10 V		±0.005%	±0.025%
		G = 10, V_O = ±10 V		±0.025%	±0.15%
		G = 100, V_O = ±10 V		±0.025%	±0.15%
		G = 1000, V_O = ±10 V		±0.05%
	Gain error drift⁽⁵⁾	G = 1, T_A = –40°C to 125°C, V_O = ±10 V			±5	ppm/°C
	Gain error drift⁽⁵⁾	G > 1, T_A = –40°C to 125°C, V_O = ±10 V			±35	ppm/°C
	Gain nonlinearity	G = 1 to 10, V_O = –10 V to 10 V, R_L = 10 kΩ		1	10	ppm
		G = 100, V_O = –10 V to 10 V, R_L = 10 kΩ			15
		G = 1000, V_O = –10 V to 10 V, R_L = 10 kΩ		10
		G = 1 to 100, V_O = –10 V to 10 V, R_L = 2 kΩ		30
OUTPUT
	Voltage swing		(V–) + 0.15		(V+) – 0.15	V
	Load capacitance stability			1000		pF
Z_O	Closed-loop output impedance	f = 10 kHz		5.0		Ω
I_SC	Short-circuit current	Continuous to V_S / 2		±20		mA
FREQUENCY RESPONSE
BW	Bandwidth, –3 dB	G = 1		2.0		MHz
		G = 10		890		kHz
		G = 100		270
		G = 1000		30
SR	Slew rate	G = 1, V_O = ±10 V		0.9		V/µs
t_S	Settling time	0.01%, G = 1 to 100, V_STEP = 10 V		12		µs
		0.01%, G = 1000, V_STEP = 10 V		40
		0.001%, G = 1 to 100, V_STEP = 10 V		16
		0.001%, G = 1000, V_STEP = 10 V		60
REFERENCE INPUT
R_IN	Input impedance			40		kΩ
	Voltage range		(V–)		(V+)	V
	Gain to output			1		V/V
	Reference gain error			0.01%
POWER SUPPLY
I_Q	Quiescent current	V_IN = 0 V		350	385	µA
I_Q	Quiescent current	V_IN = 0 V, T_A = –40°C to 125°C			520	µA

(1) Total offset, referred-to-input (RTI): V_OS = (V_OSI) + (V_OSO / G).

(2) Specified by characterization.

(3) Offset drifts are uncorrelated. Input-referred offset drift is calculated using: ΔV_OS(RTI) = √[ΔV_OSI² + (ΔV_OSO/ G)²]

(4) Input voltage range of the INA818 input stage. The input range depends on the common-mode voltage, differential voltage, gain, and reference voltage. See Typical Characteristic curves Figure 51 through Figure 54 for more information.

(5) The values specified for G > 1 do not include the effects of the external gain-setting resistor, R_G.

(6) Total RTI voltage noise is equal to: e_N(RTI) = √[e_NI² + (e_NO/ G)²]