When a master drives SDA1 low, SDA2 follows after a certain delay in the transmit direction. When SDA2 turns low it also causes the output of buffer B to turn low but at a higher 0.65 V level. This level cannot be observed immediately as it is overwritten by the lower low-level of the master.

However, when the master releases SDA1, the voltage potential increases and first must pass the upper input threshold of the comparator, V_IHT1, to release SDA2. SDA1 then increases further until it reaches the buffered output level of V_OL1 = 0.65 V, maintained by the receive path. When comparator C turns high, SDA2 is released after the delay in transmit direction. It takes another receive delay until B’s output turns high and fully releases SDA1 to move toward VCC1 potential.