7.5.1.1 SPI Description

A typical serial interface transaction begins with an 8-bit instruction that is comprised of a read-write (R/W) bit (MSB, R = 1) and a 7-bit address of the register followed by a data field that is typically 8 bits. However, the data field can be extended to a multiple of 8 bits by providing sufficient SPI clocks. See the Extended SPI Transactions section.

Figure 16. Serial Interface Protocol

Each assertion of the chip select bar (CSB) begins a new register access. The R/W bit in the command field configures the direction of the access. A value of 0 indicates a write operation, and a value of 1 indicates a read operation. All output data is driven on the falling edge of the serial clock SCLK, and all input data is sampled on the rising edge of the serial clock SCLK. Data is written into the register on the rising edge of the 16th clock. Deasserting the CSB pin after the 16th clock is required. No data write occurs if the CSB pin is deasserted before the 16th clock.