8.3.1 Buck Current Regulators

The buck regulator is unique among non-isolated topologies due to the direct connection of the inductor to the load during the entire switching cycle. An inductor will control the rate of change of current that flows through it, therefore a direct connection to the load is excellent for current regulation. A buck current regulator, using the LM3409/09HV, is shown in the Application and Implementation section. During the time that the PFET (Q1) is turned on (t_ON), the input voltage charges up the inductor (L1). When Q1 is turned off (t_OFF), the re-circulating diode (D1) becomes forward biased and L1 discharges. During both intervals, the current is supplied to the load keeping the LEDs forward biased. Figure 19 shows the inductor current (i_L(t)) waveform for a buck converter operating in CCM.

The average inductor current (I_L) is equal to the average output LED current (I_LED), therefore if I_L is tightly controlled, I_LED will be well regulated. As the system changes input voltage or output voltage, duty cycle (D) is varied to regulate I_L and ultimately I_LED. For any buck regulator, D is simply the conversion ratio divided by the efficiency (η):

Equation 1.

Figure 19. Ideal CCM Buck Converter Inductor Current i_L(t)

8.3.2 Controlled Off-Time (COFT) Architecture

The COFT architecture is used by the LM3409/09HV to control I_LED. It is a combination of peak current detection and a one-shot off-timer that varies with output voltage. D is indirectly controlled by changes in both t_OFF and t_ON, which vary depending on the operating point. This creates a variable switching frequency over the entire operating range. This type of hysteretic control eliminates the need for control loop compensation necessary in many switching regulators, simplifying the design process and providing fast transient response.

8.3.2.1 Adjustable Peak Current Control

At the beginning of a switching period, PFET Q1 is turned on and inductor current increases. Once peak current is detected, Q1 is turned off, the diode D1 forward biases, and inductor current decreases. Figure 20 shows how peak current detection is accomplished using the differential voltage signal created as current flows through the current setting resistor (R_SNS). The voltage across R_SNS (V_SNS) is compared to the adjustable current sense threshold (V_CST) and Q1 is turned off when V_SNS exceeds V_CST, providing that t_ON is greater than the minimum possible t_ON (typically 115ns).

Figure 20. Peak Current Control Circuit

There are three different methods to set the current sense threshold (V_CST) using the multi-function IADJ pin:

1. IADJ pin left open: 5 µA internal current source biases the Zener diode and clamps the IADJ pin voltage (V_ADJ) at 1.24 V causing the maximum threshold voltage:
Equation 2.
2. External voltage (V_ADJ) of 0 V to 1.24 V: Apply to the IADJ pin to adjust V_CST from 0V to 248mV. If the V_ADJ voltage is adjustable, analog dimming can be achieved.
3. External resistor (R_EXT) placed from IADJ pin to ground: 5 µA current source sets the V_ADJ voltage and corresponding threshold voltage:
Equation 3.

8.3.2.2 Controlled Off-Time

Once Q1 is turned off, it remains off for a constant time (t_OFF) which is preset by an external resistor (R_OFF), an external capacitor (C_OFF), and the output voltage (V_O) as shown in Figure 21. Because I_LED is tightly regulated, V_O will remain nearly constant over widely varying input voltage and temperature yielding a nearly constant t_OFF.

Figure 21. Off-Time Control Circuit

At the start of t_OFF, the voltage across C_OFF (v_COFF(t)) is zero and the capacitor begins charging according to the time constant provided by R_OFF and C_OFF. When v_COFF(t) reaches the off-time threshold (V_OFT = 1.24 V), then the off-time is terminated and v_COFF(t) is reset to zero. t_OFF is calculated as follows:

Equation 4.

In reality, there is typically 20 pF parasitic capacitance at the off-timer pin in parallel with C_OFF, which is accounted for in the calculation of t_OFF. Also, it should be noted that the t_OFF equation has a preceding negative sign because the result of the logarithm should be negative for a properly designed circuit. The resulting t_OFF is a positive value as long as V_O > 1.24 V. If V_O < 1.24 V, the off-timer cannot reach V_OFT and an internally limited maximum off-time (typically 300 µs) will occur.

Figure 22. Exponential Charging Function v_COFF(t)

Although the t_OFF equation is non-linear, t_OFF is actually very linear in most applications. Ignoring the 20-pF parasitic capacitance at the COFF pin, v_COFF(t) is plotted in Figure 22. The time derivative of v_COFF(t) can be calculated to find a linear approximation to the t_OFF equation:

Equation 5.

When t_OFF << R_OFF x C_OFF (equivalent to when V_O >> 1.24V), the slope of the function is essentially linear and t_OFF can be approximated as a current source charging C_OFF:

Equation 6.

Using the actual t_OFF equation, the inductor current ripple (Δi_L-PP) of a buck current regulator operating in CCM is:

Equation 7.

Using the t_OFF approximation, the equation is reduced to:

Equation 8.

NOTE

Δi_L-PP is independent of both V_IN and V_O when in CCM.

The Δi_L-PP approximation only depends on R_OFF, C_OFF, and L1, therefore the ripple is essentially constant over the operating range as long as V_O >> 1.24V (when the t_OFF approximation is valid). An exception to the t_OFF approximation occurs if the IADJ pin is used to analog dim. As the LED/inductor current decreases, the converter will eventually enter DCM and the ripple will decrease with the peak current threshold. The approximation shows how the LM3409/09HV achieves constant ripple over a wide operating range, however t_OFF should be calculated using the actual equation first presented.

8.3.3 Average LED Current

For a buck converter, the average LED current is simply the average inductor current.

Figure 23. Sense Voltage v_SNS(t)

Using the COFT architecture, the peak transistor current (I_T-MAX) is sensed as shown in Figure 23, which is equal to the peak inductor current (I_L-MAX) given by the following equation:

Equation 9.

Because I_L-MAX is set using peak current control and Δi_L-PP is set using the controlled off-timer, I_L and correspondingly I_LED can be calculated as follows:

Equation 10.

The threshold voltage V_CST seen by the high-side sense comparator is affected by the comparator’s input offset voltage, which causes an error in the calculation of I_L-MAX and ultimately I_LED. To mitigate this problem, the polarity of the comparator inputs is swapped every cycle, which causes the actual I_L-MAX to alternate between two peak values (I_L-MAXH and I_L-MAXL), equidistant from the theoretical I_L-MAX as shown in Figure 24. I_LED remains accurate through this averaging.

Figure 24. Inductor Current i_L(t) Showing I_L-MAX Offset

8.3.4 Inductor Current Ripple

Because the LM3409/09HV swaps the polarity of the differential current sense comparator every cycle, a minimum inductor current ripple (Δi_L-PP) is necessary to maintain accurate I_LED regulation. Referring to Figure 24, the first t_ON is terminated at the higher of the two polarity-swapped thresholds (corresponding to I_L-MAXH). During the following t_OFF, i_L decreases until the second t_ON begins. If t_OFF is too short, then as the second t_ON begins, i_L will still be above the lower peak current threshold (corresponding to I_L-MAXL) and a minimum t_ON pulse will follow. This will result in degraded I_LED regulation. The minimum inductor current ripple (Δi_L-PP-MIN) should adhere to the following equation to ensure accurate I_LED regulation:

Equation 11.

8.3.5 Switching Frequency

The switching frequency is dependent upon the actual operating point (V_IN and V_O). V_O will remain relatively constant for a given application, therefore the switching frequency will vary with V_IN (frequency increases as V_IN increases). The target switching frequency (f_SW) at the nominal operating point is selected based on the tradeoffs between efficiency (better at low frequency) and solution size/cost (smaller at high frequency). The off-time of the LM3409/09HV can be programmed for switching frequencies up to 5 MHz (theoretical limit imposed by minimum t_ON). In practice, switching frequencies higher than 1MHz may be difficult to obtain due to gate drive limitations, high input voltage, and thermal considerations.

At CCM operating points, f_SW is defined as:

Equation 12.

At DCM operating points, f_SW is defined as:

Equation 13.

In the CCM equation, it is apparent that the efficiency (η) factors into the switching frequency calculation. Efficiency is hard to estimate and, because switching frequency varies with input voltage, accuracy in setting the nominal switching frequency is not critical. Therefore, a general rule of thumb for the LM3409/09HV is to assume an efficiency between 85% and 100%. When approximating efficiency to target a nominal switching frequency, the following condition must be met:

Equation 14.

8.3.6 PWM Dimming Using the EN Pin

The enable pin (EN) is a TTL compatible input for PWM dimming of the LED. A logic low (below 0.5V) at EN will disable the internal driver and shut off the current flow to the LED array. While the EN pin is in a logic low state the support circuitry (driver, bandgap, V_CC regulator) remains active to minimize the time needed to turn the LED array back on when the EN pin sees a logic high (above 1.74 V).

Figure 25 shows the LED current (i_LED(t)) during PWM dimming where duty cycle (D_DIM) is the percentage of the dimming period (T_DIM) that the PFET is switching. For the remainder of T_DIM, the PFET is disabled. The resulting dimmed average LED current (I_DIM-LED) is:

Equation 15.

The LED current rise and fall times (which are limited by the slew rate of the inductor as well as the delay from activation of the EN pin to the response of the external PFET) limit the achievable T_DIM and D_DIM. In general, dimming frequency should be at least one order of magnitude lower than the steady state switching frequency to prevent aliasing. However, for good linear response across the entire dimming range, the dimming frequency may need to be even lower.

8.3.7 High Voltage Negative BIAS Regulator

The LM3409/09HV contains an internal linear regulator where the steady state VCC pin voltage is typically 6.2 V below the voltage at the VIN pin. The VCC pin should be bypassed to the VIN pin with at least 1µF of ceramic capacitance connected as close as possible to the IC.

8.3.8 External Parallel FET PWM Dimming

Figure 26. Ideal LED Current i_LED(t) During Parallel FET Dimming

Any buck topology LED driver is a good candidate for parallel FET dimming because high slew rates are achievable, due to the fact that no output capacitance is required. This allows for much higher dimming frequencies than are achievable using the EN pin. When using external parallel FET dimming, a situation can arise where maximum off-time occurs due to a shorted output. To mitigate this situation, a secondary voltage (V_DD) should be used as shown in Figure 27.

Figure 27. External Parallel FET Dimming Circuit

A small diode is connected in series with the off time resistor calculated for nominal operation from the output, R_OFF1. Then connect a small diode from the secondary voltage along with another resistor, R_OFF2. The secondary voltage can be any voltage as long as it is greater than 2V. The value of ROFF2 can be calculated using Equation 16.

Equation 16.

The ideal LED current waveform i_LED(t) during parallel FET PWM dimming is very similar to the EN pin PWM dimming shown previously. The LED current does not rise and fall infinitely fast as shown in Figure 26 however with this method, only the speed of the parallel Dim FET ultimately limits the dimming frequency and dimming duty cycle. This allows for much faster PWM dimming than can be attained with the EN pin.

8.4.1 Low-Power Shutdown

The LM3409/09HV can be placed into a low-power shutdown (typically 110 µA) by grounding the EN terminal (any voltage below 0.5 V) until V_CC drops below the V_CC UVLO threshold (typically 3.73 V). During normal operation this terminal should be tied to a voltage above 1.74 V and below absolute maximum input voltage rating.

8.4.2 Thermal Shutdown

Internal thermal shutdown circuitry is provided to protect the IC in the event that the maximum junction temperature is exceeded. The threshold for thermal shutdown is 160°C with 15°C of hysteresis (both values typical). During thermal shutdown the PFET and driver are disabled.