ZHCSPC5 October 2022 LM51231-Q1
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Device Enable/Disable (EN, VH Pin)
- 7.3.2 High Voltage VCC Regulator (BIAS, VCC Pin)
- 7.3.3 Light Load Switching Mode Selection (MODE Pin)
- 7.3.4 VOUT Range Selection (RANGE Pin)
- 7.3.5 Line Undervoltage Lockout (UVLO Pin)
- 7.3.6 Fast Restart using VCC HOLD (VH Pin)
- 7.3.7 Adjustable Output Regulation Target (VOUT, TRK, VREF Pin)
- 7.3.8 Overvoltage Protection (VOUT Pin)
- 7.3.9 Power Good Indicator (PGOOD Pin)
- 7.3.10 Dynamically Programmable Switching Frequency (RT)
- 7.3.11 External Clock Synchronization (SYNC Pin)
- 7.3.12 Programmable Spread Spectrum (DITHER Pin)
- 7.3.13 Programmable Soft-start (SS Pin)
- 7.3.14 Wide Bandwidth Transconductance Error Amplifier and PWM (TRK, COMP Pin)
- 7.3.15 Current Sensing and Slope Compensation (CSP, CSN Pin)
- 7.3.16 Constant Peak Current Limit (CSP, CSN Pin)
- 7.3.17 Maximum Duty Cycle and Minimum Controllable On-time Limits
- 7.3.18 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LO, HO, HB Pin)
- 7.3.19 Thermal Shutdown Protection
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
7.3.13 Programmable Soft-start (SS Pin)
The soft-start feature helps the converter gradually reach the steady state operating point. To reduce start-up stresses and surges, the device regulates the error amplifier reference to the SS pin voltage or the TRK pin voltage (VTRK), whichever is lower.
The internal 20-μA soft-start (ISS) current turns on 120 μs after the VCC pin crosses VVCC-UVLO. ISS gradually increases the voltage on an external soft-start capacitor (CSS). This results in a gradual rise of the output voltage.
In FPWM mode, the device forces diode emulation while the SS pin voltage is less than 1.5 V. When the SS pin voltage is greater than 1.5 V, the device changes the high-side negative current limit threshold from VZCD-DE to VI-HS-NEG.
Figure 7-12 Soft Start and Smooth Transition to
FPWMIn boost topology, the soft-start time (tSS) varies with the input supply voltage because the boost output voltage is equal to the boost input voltage at the beginning of the soft-start switching. tSS in boost topology is calculated in Equation 10.
In general, it is recommended to choose a soft-start time long enough so that the converter can start up without going into an overcurrent state. If the device is used for a pre-boost in automotive application, it is recommended to use 100-pF CSS to reach steady state as soon as possible.
The device also features an internal SS-to-FB clamp (VSS-FB), which clamps SS 55 mV above FB and is activated if 256 consecutive switching cycles occur with current limit. The SS-to-FB clamp is deactivated if 32 consecutive switching cycles occur without exceeding the current limit threshold. This clamp helps to minimize surges after output shorts or over load situations. The device can enter deep sleep mode when SS is greater than 1.5 V. It is not recommended to pulldown SS to stop switching.