ZHCSFO3D November 2016 – August 2021 LM5170-Q1
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 说明（续）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Bias Supply (VCC, VCCA)
- 8.3.2 Undervoltage Lockout (UVLO) and Master Enable or Disable
- 8.3.3 High Voltage Input (VIN, VINX)
- 8.3.4 Current Sense Amplifier
- 8.3.5 Control Commands
- 8.3.6 Channel Current Monitor (IOUT1, IOUT2)
- 8.3.7 Cycle-by-Cycle Peak Current Limit (IPK)
- 8.3.8 Error Amplifier
- 8.3.9 Ramp Generator
- 8.3.10 Soft Start
- 8.3.11 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT)
- 8.3.12 PWM Comparator
- 8.3.13 Oscillator (OSC)
- 8.3.14 Synchronization to an External Clock (SYNCIN, SYNCOUT)
- 8.3.15 Diode Emulation
- 8.3.16 Power MOSFET Failure Detection and Failure Protection (nFAULT, BRKG, BRKS)
- 8.3.17 Overvoltage Protection (OVPA, OVPB)
- 8.4 Device Functional Modes
- 8.5 Programming
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1
60-A, Dual-Phase, 48-V to 12-V Bidirectional Converter
- 9.2.1.1 Design Requirements
- 9.2.1.2
Detailed Design Procedure
- 9.2.1.2.1 Determining the Duty Cycle
- 9.2.1.2.2 Oscillator Programming
- 9.2.1.2.3 Power Inductor, RMS and Peak Currents
- 9.2.1.2.4 Current Sense (RCS)
- 9.2.1.2.5 Current Setting Limits (ISETA or ISETD)
- 9.2.1.2.6 Peak Current Limit
- 9.2.1.2.7 Power MOSFETS
- 9.2.1.2.8 Bias Supply
- 9.2.1.2.9 Boot Strap
- 9.2.1.2.10 RAMP Generators
- 9.2.1.2.11 OVP
- 9.2.1.2.12 Dead Time
- 9.2.1.2.13 IOUT Monitors
- 9.2.1.2.14 UVLO Pin Usage
- 9.2.1.2.15 VIN Pin Configuration
- 9.2.1.2.16 Loop Compensation
- 9.2.1.2.17 Soft Start
- 9.2.1.2.18 ISET Pins
- 9.2.1.3 Application Curves
- 9.2.1
60-A, Dual-Phase, 48-V to 12-V Bidirectional Converter
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
9.2.1.2.8 Bias Supply
The LM5170-Q1 requires an external 10- to 12-V VCC bias supply to operate. If not available in the system, the user can generate it from the LV-port using a buck-boost or SEPIC converter, or from the HV-port using a buck converter. Refer to the Texas Instruments LM25118-Q1 and LM5118-Q1 to implement a buck-boost converter, or LM5001-Q1 to implement a SEPIC converter, or the LM5160-Q1 and LM5161-Q1 to implement a buck converter.
The total load current of the bias supply is mainly determined by the total MOSFET gate charge Qg. Assume the system employs multiple LM5170-Q1s to implement M number of phases, and each phase uses N number of MOSFETs in parallel as one switch. There are 2× N MOSFETs per phase to drive. Then the total current to drive these MOSFETs through VCC bias supply is determined by Equation 60.
where
- 5 mA is the worst case maximum current used by the control logic circuit of each phase.
In an example of a four-phase system employing two parallelled MOSFETs for one switch, where M = 4, N = 2, Qg = 100 nC, and Fsw = 100 KHz, the bias supply should be able to support at least the following total load current:
In an example of an eight-phase system employing the same parallel MOSFETs for one switch, the bias supply should be able to support the following total load current:
The VCC AC bypass ceramic capacitor CVCC = 1 to approximately 2.2 µF, rated at least 16 V, must be placed close to the VCC and PGND pins. Similarly, a ceramic capacitor CVCCA = 1 µF, rated at least 16 V, must be placed close to the VCCA and AGND pins. Place a 24-Ω resistor between VCC and VCCA pins.