ZHCSLD0B May   2020  – June 2021 LM62435-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 计时特性
    7. 7.7 Systems Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  EN Uses for Enable and VIN UVLO
      2. 8.3.2  MODE/SYNC Pin Operation
        1. 8.3.2.1 Level-Dependent MODE/SYNC Pin Control
        2. 8.3.2.2 Pulse-Dependent MODE/SYNC Pin Control
        3. 8.3.2.3 Clock Locking
      3. 8.3.3  PGOOD Output Operation
      4. 8.3.4  Internal LDO, VCC UVLO, and BIAS Input
      5. 8.3.5  Bootstrap Voltage and VCBOOT-UVLO (CBOOT Pin)
      6. 8.3.6  Adjustable SW Node Slew Rate
      7. 8.3.7  Spread Spectrum
      8. 8.3.8  Soft Start and Recovery From Dropout
      9. 8.3.9  Output Voltage Setting
      10. 8.3.10 Overcurrent and Short Circuit Protection
      11. 8.3.11 Thermal Shutdown
      12. 8.3.12 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
        1. 8.4.3.1 CCM Mode
        2. 8.4.3.2 Auto Mode - Light Load Operation
          1. 8.4.3.2.1 Diode Emulation
          2. 8.4.3.2.2 Frequency Reduction
        3. 8.4.3.3 FPWM Mode - Light Load Operation
        4. 8.4.3.4 Minimum On-time (High Input Voltage) Operation
        5. 8.4.3.5 Dropout
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Choosing the Switching Frequency
        2. 9.2.2.2  Setting the Output Voltage
        3. 9.2.2.3  Inductor Selection
        4. 9.2.2.4  Output Capacitor Selection
        5. 9.2.2.5  Input Capacitor Selection
        6. 9.2.2.6  BOOT Capacitor
        7. 9.2.2.7  BOOT Resistor
        8. 9.2.2.8  VCC
        9. 9.2.2.9  BIAS
        10. 9.2.2.10 CFF and RFF Selection
        11. 9.2.2.11 External UVLO
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground and Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.3.5 Bootstrap Voltage and VCBOOT-UVLO (CBOOT Pin)

The driver of the High-Side (HS) switch requires bias higher than VIN. The capacitor, CBOOT, connected between CBOOT and SW, works as a charge pump to boost voltage on the CBOOT pin to SW + VCC. A boot diode is integrated on the LM62435-Q1 die to minimize external component count. It is recommended that a 100-nF capacitor rated for 10 V or higher is used. The VBOOT_UVLO threshold (2.1 V typ.) is designed to maintain proper HS switch operation. If the CBOOT capacitor voltage drops below VBOOT_UVLO, then the device initiates a charging sequence, turning on the low-side switch before attempting to turn on the HS switch.
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |